#14 Won't parse genvars outside generate blocks

devel
closed-fixed
nobody
5
2006-04-10
2005-12-02
Anonymous
No

Submitted by:

mailto:pdbain@altera.com

-------------------------------------

The following code:

module Nbit_adderIndex (co, sum, a, b, ci);

parameter SIZE = 4;
output [SIZE-1:0] sum;
output co;
input [SIZE-1:0] a, b;
input ci;
wire [SIZE:0] c;

genvar i;
assign c[0] = ci;

assign co = c[SIZE];

generate
for(i=0; i<SIZE; i=i+1)
begin:addbit
wire n1,n2,n3; //internal nets
xor g1 (n1 ,a[i] ,b[i]);
xor g2 (sum[i] ,n1 ,c[i]);
and g3 (n2 , a[i] ,b[i]);
and g4 (n3 , n1 ,c[i]);
or g5 (c[i+1] ,n2 ,n3);
end
endgenerate

endmodule

dies:

bash-2.05b$ iverilog generate1.v
generate1.v:10: syntax error
generate1.v:10: error: Invalid module instantiation

bash-2.05b$ iverilog -V
Icarus Verilog version 0.8.2 ($Name: v0_8_2 $)

According to the 1364-2001 (28 sept 2001),
genvar_declaration is a
module_or_generate_item_declaration, which is a
module_or_generate_item, which is a module_item, which
is a valid part of a module_declaration. This code
compiles fine in Modelsim.

Discussion

  • Stephen Williams

    • milestone: 530319 --> devel
    • status: open --> pending
     
  • Stephen Williams

    Logged In: YES
    user_id=97566

    Icarus Verilog 0.8 does not support generate statements, so
    I've changed the group to devel. The development source also
    does not support generate statements, so I've changed the
    status to reflect that this report is not closed, but not
    going to be addressed until generate statements are added.

     
  • SourceForge Robot

    • status: pending --> closed
     
  • SourceForge Robot

    Logged In: YES
    user_id=1312539

    This Tracker item was closed automatically by the system. It was
    previously set to a Pending status, and the original submitter
    did not respond within 14 days (the time period specified by
    the administrator of this Tracker).

     
  • Stephen Williams

    • status: closed --> open-postponed
     
  • Stephen Williams

    • status: open-postponed --> closed-fixed
     
  • Stephen Williams

    Logged In: YES
    user_id=97566

    I've created the new snapshot 20060409 that fixes this
    problem, and many others. See the announcement for the
    20060409 snapshot in the geda-dev mailing list or the news
    link from the Icarus Verilog home page.

     
  • Nobody/Anonymous

    fE6xjv <a href="http://njtadixtynyl.com/">njtadixtynyl</a>, [url=http://wtgikzlgyqjt.com/]wtgikzlgyqjt[/url], [link=http://ccbdbscejcni.com/]ccbdbscejcni[/link], http://pmmznqqtrfun.com/

     

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