Memory blocks describe a block of memory that can be mapped into a [map], for use by code running in that map.
The entries in a memory block are commonly very similar to the entry to be stored in the translation tables used by the MMU, and the concept has a lot in common with the Translate Lookaside Buffers of the ARM processor. Ideally, I would like the processor to allow me to directly write TLB entries, but that doesn´t seem to be an option. Instead, I intend to keep the translation tables almost empty (i.e. full of invalid entries - with bits 0:1 zero), fill in table entries as aborts occur, and clear them again on the next abort or map change.
According to the ARM-ARM, the MMU counts as a separate observer (B2.7.3), so any writes need to be flushed to memory before returning from a Page or Section Translation fault. However, section 11.3 of the OMAP 35xx TRM (rev. U), "On-Chip Memory Subsystem", seems to indicate that the on-board SRAM (which is where the page tables will be located) is fast ("Fully pipelined, one 32-bit access per cycle") and so I intend to map the data uncached and shareable.
The Domain feature of the ARM architecture is not used to disable access to areas of the virtual memory map, since the domain check occurs only after the TLB has been written (ARM-ARM Figure B4-2 Sequence for checking faults) and the overhead of cleaning the TLB probably exceeds the time taken to invalidate the page table memory.