iceboy Code

GameBoy clone

Status: Alpha

Brought to you by: m_singer

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File	Date	Author	Commit
doc	2018-11-11	Michael Singer	[1c3325] fix DMG model in test results
ice40_viewer	2018-10-12	Michael Singer	[041c16] move files into sub directory
m4	2021-01-27	Michael Singer	[4740d7] Simulated CPU executes code from stdin
pcbs	2025-03-29	Michael Singer	[c86b7e] Ignore *.kicad_prl
sch	2018-04-03	Michael Singer	[97be1f] add kicad schematics
sim	2021-03-14	Michael Singer	[3bf5b5] SM83: Fix debug interface for new CPU
src	2021-03-14	Michael Singer	[29709d] Convert to SystemVerilog
tests	2021-03-07	Michael Singer	[af63d3] Add formal tests for load instructions
.gitattributes	2022-11-20	Michael Singer	[0fb8ec] Cleanup github language stats
.gitignore	2020-09-05	Michael Singer	[acaa1b] implement tests for new ALU
AUTHORS	2018-10-13	Michael Singer	[9abe76] build with autotools
INSTALL	2018-10-13	Michael Singer	[9abe76] build with autotools
LICENSE	2021-08-18	Michael Singer	[57e6bc] Switch to CERN-OHL-W v2 license
Makefile.am	2021-01-17	Michael Singer	[76abb0] Simulate new CPU with code by yosys write_cxxrtl
README	2021-08-18	Michael Singer	[57e6bc] Switch to CERN-OHL-W v2 license
configure.ac	2021-03-14	Michael Singer	[29709d] Convert to SystemVerilog

Read Me

iceboy
------

http://iceboy.a-singer.de/
https://github.com/msinger/iceboy/
https://sourceforge.net/projects/iceboy/

Licensed under CERN-OHL-W v2
https://cern-ohl.web.cern.ch/

The goal of this project is to implement a GameBoy in Verilog using the open
source IceStorm tools for Lattice iCE40HX-8K FPGAs. You can get the tools from
here:
  http://www.clifford.at/icestorm/

iceboy Code

GameBoy clone

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