[HPPAQEMU-CVS] hppaqemu/target-hppa cpu.h,1.5,1.6 op.c,1.27,1.28

[Stuart B. <zu...@us...>]

Update of /cvsroot/hppaqemu/hppaqemu/target-hppa
In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv20577

Modified Files:
	cpu.h op.c 
Log Message:
Fix PSW definitions, based on a patch by Tomonori Yamane.


Index: cpu.h
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/cpu.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- cpu.h	9 Mar 2007 15:57:31 -0000	1.5
+++ cpu.h	20 Apr 2007 14:21:57 -0000	1.6
@@ -68,39 +68,39 @@
 /* the shadow registers map to the following general registers */
 // int shrmap[] = { 1, 6, 9, 16, 17, 24, 25 };
 
-#define PSW_Y   0x00000001
-#define PSW_Z   0x00000002
-#define PSW_W   0x00000010
-#define PSW_E   0x00000020
-#define PSW_S   0x00000040
-#define PSW_T   0x00000080
-#define PSW_H   0x00000100
-#define PSW_L   0x00000200
-#define PSW_N   0x00000400
-#define PSW_X   0x00000800
-#define PSW_B   0x00001000
-#define PSW_C   0x00002000
-#define PSW_V   0x00004000
-#define PSW_M   0x00008000
-#define PSW_CB  0x00ff0000
-#define PSW_CB0 0x00010000
-#define PSW_CB1 0x00020000
-#define PSW_CB2 0x00040000
-#define PSW_CB3 0x00080000
-#define PSW_CB4 0x00100000
-#define PSW_CB5 0x00200000
-#define PSW_CB6 0x00400000
-#define PSW_CB7 0x00800000
-#define PSW_O   0x01000000
-#define PSW_G   0x02000000
-#define PSW_F   0x04000000
-#define PSW_R   0x08000000
-#define PSW_Q   0x10000000
-#define PSW_P   0x20000000
-#define PSW_D   0x40000000
-#define PSW_I   0x80000000
+#define PSW_I   0x00000001
+#define PSW_D   0x00000002
+#define PSW_P   0x00000004
+#define PSW_Q   0x00000008
+#define PSW_R   0x00000010
+#define PSW_F   0x00000020
+#define PSW_G   0x00000040
+#define PSW_O   0x00000080
+#define PSW_CB  0x0000ff00
+#define PSW_CB0 0x00000100
+#define PSW_CB1 0x00000200
+#define PSW_CB2 0x00000400
+#define PSW_CB3 0x00000800
+#define PSW_CB4 0x00001000
+#define PSW_CB5 0x00002000
+#define PSW_CB6 0x00004000
+#define PSW_CB7 0x00008000
+#define PSW_M   0x00010000
+#define PSW_V   0x00020000
+#define PSW_C   0x00040000
+#define PSW_B   0x00080000
+#define PSW_X   0x00100000
+#define PSW_N   0x00200000
+#define PSW_L   0x00400000
+#define PSW_H   0x00800000
+#define PSW_T   0x01000000
+#define PSW_S   0x02000000
+#define PSW_E   0x04000000
+#define PSW_W   0x08000000
+#define PSW_Z   0x40000000
+#define PSW_Y   0x80000000
 
-#define PSW_CB7_SHIFT	8	/* CHECK */
+#define PSW_CB_SHIFT    8
 
 typedef struct CPUHPPAState {
     target_ulong gr[32];  /* General Registers */

Index: op.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v
retrieving revision 1.27
retrieving revision 1.28
diff -u -d -r1.27 -r1.28
--- op.c	21 Mar 2007 21:17:50 -0000	1.27
+++ op.c	20 Apr 2007 14:21:57 -0000	1.28
@@ -455,7 +455,7 @@
     carry &= 0x000000ff;  /* 000000000000000000000000abcdefgh */
 
     env->psw &= ~PSW_CB;
-    env->psw |= carry << PSW_CB7_SHIFT;
+    env->psw |= carry << PSW_CB_SHIFT;
 }
 
 void OPPROTO op_add_T1_T0(void)
@@ -490,7 +490,7 @@
     carry &= 0x000000ff;  /* 000000000000000000000000abcdefgh */
 
     env->psw &= ~PSW_CB;
-    env->psw |= carry << PSW_CB7_SHIFT;
+    env->psw |= carry << PSW_CB_SHIFT;
 }
 
 /* gen_op_add_T1_imm(1) -- for ADDC and ADDCO */
@@ -624,7 +624,7 @@
     borrow &= 0x000000ff;   /* 000000000000000000000000abcdefgh */
 
     env->psw &= ~PSW_CB;
-    env->psw |= ~borrow << PSW_CB7_SHIFT;
+    env->psw |= ~borrow << PSW_CB_SHIFT;
 }
 
 void OPPROTO op_sub_T1_T0(void)
@@ -659,7 +659,7 @@
     borrow &= 0x000000ff;   /* 000000000000000000000000abcdefgh */
 
     env->psw &= ~PSW_CB;
-    env->psw |= ~borrow << PSW_CB7_SHIFT;
+    env->psw |= ~borrow << PSW_CB_SHIFT;
 }
 
 void OPPROTO op_ds_T1_T0(void)