[HPPAQEMU-CVS] hppaqemu/target-hppa translate.c,1.38,1.39

[Stuart B. <zu...@us...>]

Update of /cvsroot/hppaqemu/hppaqemu/target-hppa
In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv14411

Modified Files:
	translate.c 
Log Message:
Implement and use assemble_17() and assemble_21().


Index: translate.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v
retrieving revision 1.38
retrieving revision 1.39
diff -u -d -r1.38 -r1.39
--- translate.c	21 Mar 2007 23:37:38 -0000	1.38
+++ translate.c	22 Mar 2007 15:48:50 -0000	1.39
@@ -100,6 +100,18 @@
     return (y << 11) | ((x & 1) << 10) | ((x >> 1) & ~(~0 << 10));
 }
 
+static uint32_t assemble_17(uint32_t x, uint32_t y, uint32_t z) {
+    return (z << 16) | (x << 11) | ((y & 1) << 10) | ((y >> 1) & ~(~0 << 10));
+}
+
+static uint32_t assemble_21(uint32_t x) {
+    return ((x & 1) << 20) |
+           (((x >> 1) & ~(~0 << 11)) << 9) |
+           (((x >> 14) & ~(~0 << 2)) << 7) |
+           (((x >> 16) & ~(~0 << 5)) << 2) |
+           ((x >> 12) & ~(~0 << 2));
+}
+
 static GenOpFunc *gen_op_movl_TN_reg[3][32] =
 {
     {
@@ -1629,7 +1641,7 @@
             uint32_t t, im21;
             t = field(insn, 21, 5);
             if(t) {
-                im21 = field(insn, 0, 21) << (32 - 21);
+                im21 = assemble_21(field(insn, 0, 21)) << (32 - 21);
                 gen_movl_T0_im(im21);
                 gen_movl_reg_T0(t);
             }
@@ -1653,7 +1665,7 @@
         {
             uint32_t r, im21;
             r = field(insn, 21, 5);
-            im21 = field(insn, 0, 21) << (32 - 21);
+            im21 = assemble_21(field(insn, 0, 21)) << (32 - 21);
             gen_movl_T1_reg(r);
             gen_movl_T0_im(im21);
             gen_op_addl_T1_T0();
@@ -2001,12 +2013,12 @@
         {
             uint32_t b, w1, s, w2, n, w, disp;
             b = field(insn, 21, 5);
-            w1 = field_signext(insn, 16, 5);
+            w1 = field(insn, 16, 5);
             s = field(insn, 13, 3);
             w2 = field(insn, 2, 11);
             n = field(insn, 1, 1);
             w = field(insn, 0, 1);
-            disp = (((((w1 << 11) | w2) << 1) | w) << 2);
+            disp = signext(assemble_17(w1,w2,w),17) << 2;
             /*  */
 
             /* FIXME */
@@ -2019,11 +2031,11 @@
             uint32_t t, w, w1, ext3, w2, n, disp;
             ext3 = field(insn, 13, 3);
             t = field(insn, 21, 5);
-            w1 = field_signext(insn, 16, 5);
+            w1 = field(insn, 16, 5);
             w2 = field(insn, 2, 11);
             n = field(insn, 1, 1);
             w = field(insn, 0, 1);
-            disp = (((((w1 << 11) | w2) << 1) | w) << 2);
+            disp = signext(assemble_17(w1,w2,w),17) << 2;
             switch(ext3) {
                 case 0: /* BL */
                     /* TODO: dc->iaoq[1] + 4 into t */