[HPPAQEMU-CVS] hppaqemu/target-hppa op.c, 1.15, 1.16 translate.c, 1.18, 1.19

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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa
In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv6875

Modified Files:
	op.c translate.c 
Log Message:
Whitespace cleanup.


Index: translate.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v
retrieving revision 1.18
retrieving revision 1.19
diff -C2 -d -r1.18 -r1.19
*** translate.c	12 Mar 2007 15:50:26 -0000	1.18
--- translate.c	12 Mar 2007 15:54:19 -0000	1.19
***************
*** 625,633 ****
              gen_op_goto_tb1(TBPARAM(tb));
          gen_op_save_pc(pc, npc);
! 	gen_movl_T0_im((long)tb + tb_num);
          gen_op_exit_tb();
      } else {
          gen_op_save_pc(pc, npc);
! 	gen_movl_T0_im(0);
          gen_op_exit_tb();
      }
--- 625,633 ----
              gen_op_goto_tb1(TBPARAM(tb));
          gen_op_save_pc(pc, npc);
!         gen_movl_T0_im((long)tb + tb_num);
          gen_op_exit_tb();
      } else {
          gen_op_save_pc(pc, npc);
!         gen_movl_T0_im(0);
          gen_op_exit_tb();
      }
***************
*** 701,716 ****
             generate an exception */
          if (env->singlestep_enabled)
!     	    break;
      }
      if (env->singlestep_enabled) 
      {
          save_state(dc);
! 	gen_op_debug();
! 	goto exit_gen_loop;
      }
      else if (!dc->is_br)
      {
          save_state(dc);
! 	gen_goto_tb(dc, 0, dc->iaoq[0], dc->iaoq[1]);
      }
      gen_op_exit_tb();
--- 701,716 ----
             generate an exception */
          if (env->singlestep_enabled)
!             break;
      }
      if (env->singlestep_enabled) 
      {
          save_state(dc);
!         gen_op_debug();
!         goto exit_gen_loop;
      }
      else if (!dc->is_br)
      {
          save_state(dc);
!         gen_goto_tb(dc, 0, dc->iaoq[0], dc->iaoq[1]);
      }
      gen_op_exit_tb();
***************
*** 882,902 ****
      {
          case LDST_CMPLT_MB:
! 	    gen_movl_T1_reg(b);
! 	    gen_op_copy_T2_T0(); /* T2 = dx */
! 	    gen_op_addl_T1_T0(); /* offset = GR[b] + dx */
! 	    gen_op_addl_T2_T1(); /* GR[b] += dx */
! 	    gen_movl_reg_T1(b);
! 	    break;
          case LDST_CMPLT_MA:
! 	    gen_movl_T1_reg(b);
! 	    gen_op_copy_T2_T1(); /* T2 = GR[b] */
! 	    gen_op_addl_T0_T1(); /* GR[b] += dx */
! 	    gen_movl_reg_T1(b);
! 	    gen_op_copy_T0_T2(); /* offset = GR[b] */
! 	    break;
! 	default:
! 	    gen_movl_T1_reg(b);
! 	    gen_op_addl_T1_T0(); /* offset = GR[b] + dx */
! 	    break;
      }
      gen_movl_T1_reg(r);
--- 882,902 ----
      {
          case LDST_CMPLT_MB:
!             gen_movl_T1_reg(b);
!             gen_op_copy_T2_T0(); /* T2 = dx */
!             gen_op_addl_T1_T0(); /* offset = GR[b] + dx */
!             gen_op_addl_T2_T1(); /* GR[b] += dx */
!             gen_movl_reg_T1(b);
!             break;
          case LDST_CMPLT_MA:
!             gen_movl_T1_reg(b);
!             gen_op_copy_T2_T1(); /* T2 = GR[b] */
!             gen_op_addl_T0_T1(); /* GR[b] += dx */
!             gen_movl_reg_T1(b);
!             gen_op_copy_T0_T2(); /* offset = GR[b] */
!             break;
!         default:
!             gen_movl_T1_reg(b);
!             gen_op_addl_T1_T0(); /* offset = GR[b] + dx */
!             break;
      }
      gen_movl_T1_reg(r);
***************
*** 910,914 ****
      uint32_t r2 = field(insn, 21, 5);
      uint32_t t = field(insn, 0, 5);
! 		 
      gen_movl_T1_reg(r1);
      gen_movl_T2_reg(r2);
--- 910,914 ----
      uint32_t r2 = field(insn, 21, 5);
      uint32_t t = field(insn, 0, 5);
! 
      gen_movl_T1_reg(r1);
      gen_movl_T2_reg(r2);
***************
*** 972,976 ****
       *   refactoring
       */
!     
      /* two possible ways to do nullification
       * easiest is probably to generate code to check the N flag on each insn
--- 972,976 ----
       *   refactoring
       */
! 
      /* two possible ways to do nullification
       * easiest is probably to generate code to check the N flag on each insn
***************
*** 1019,1023 ****
                      gen_movl_reg_T0(field(insn, 0, 5));
                      break;
!                    
                  case 0x73: /* RSM */
                      gen_op_check_priv0();
--- 1019,1023 ----
                      gen_movl_reg_T0(field(insn, 0, 5));
                      break;
! 
                  case 0x73: /* RSM */
                      gen_op_check_priv0();
***************
*** 1114,1118 ****
                      break;
                  }
!                 
                  case 0x45: /* MFCTL */
                  {
--- 1114,1118 ----
                      break;
                  }
! 
                  case 0x45: /* MFCTL */
                  {
***************
*** 1361,1371 ****
                      break;
                  case 0x08: /* STB */
! 		    gen_store(insn, gen_op_stb_raw);
! 		    break;
                  case 0x09: /* STH */
! 		    gen_store(insn, gen_op_sth_raw);
! 		    break;
                  case 0x0A: /* STW */
! 		    gen_store(insn, gen_op_stw_raw);
                      break;
  
--- 1361,1371 ----
                      break;
                  case 0x08: /* STB */
!                     gen_store(insn, gen_op_stb_raw);
!                     break;
                  case 0x09: /* STH */
!                     gen_store(insn, gen_op_sth_raw);
!                     break;
                  case 0x0A: /* STW */
!                     gen_store(insn, gen_op_stw_raw);
                      break;
  
***************
*** 1374,1378 ****
  
                  case 0x0E: /* STWA */
! 		    gen_store(insn, gen_op_stw_phys);
                      break;
  
--- 1374,1378 ----
  
                  case 0x0E: /* STWA */
!                     gen_store(insn, gen_op_stw_phys);
                      break;
  
***************
*** 1388,1392 ****
              break;
          }
!         
          case 0x04: /* SPOPn */
              break;
--- 1388,1392 ----
              break;
          }
! 
          case 0x04: /* SPOPn */
              break;
***************
*** 1395,1399 ****
          case 0x06: /* FMPYADD */
              break;
!         
          case 0x08: /* LDIL */
          {
--- 1395,1399 ----
          case 0x06: /* FMPYADD */
              break;
! 
          case 0x08: /* LDIL */
          {
***************
*** 1465,1469 ****
          case 0x0f: /* Product Specific */
              break;
!         
          case 0x10: /* LDB */
          case 0x11: /* LDH */
--- 1465,1469 ----
          case 0x0f: /* Product Specific */
              break;
! 
          case 0x10: /* LDB */
          case 0x11: /* LDH */
***************
*** 1525,1529 ****
              }
          }
!         
          case 0x1b: /* STWM */
          case 0x20: /* COMBT */
--- 1525,1529 ----
              }
          }
! 
          case 0x1b: /* STWM */
          case 0x20: /* COMBT */
***************
*** 1570,1574 ****
          case 0x2b: /* ADDIBF */
              break;
!         
          case 0x2c: /* ADDIT, ADDIOT */
          case 0x2d: /* ADDI, ADDIO */
--- 1570,1574 ----
          case 0x2b: /* ADDIBF */
              break;
! 
          case 0x2c: /* ADDIT, ADDIOT */
          case 0x2d: /* ADDI, ADDIO */
***************
*** 1595,1599 ****
              dc->is_br = 1;
              break;
!         
          case 0x34: /* Extract */
          {
--- 1595,1599 ----
              dc->is_br = 1;
              break;
! 
          case 0x34: /* Extract */
          {
***************
*** 1602,1632 ****
              switch(ext3) {
                  case 0: /* VSHD = SHRPW with SAR */
! 		    gen_movl_T0_cr(11);
! 		    gen_shrpw(insn);
! 		    break;
                  case 2: /* SHD = SHRPW */
! 		{
! 		    uint32_t sa = 31 - field(insn, 5, 5);
! 		    gen_movl_T0_im(sa);
! 		    gen_shrpw(insn);
! 		    break;
! 		}
                  case 4: /* VEXTRU = EXTRW,U with SAR */
                  case 5: /* VEXTRS = EXTRW,S with SAR */
! 		    gen_movl_T0_cr(11);
! 		    gen_extrw(insn);
! 		    break;
                  case 6: /* EXTRU = EXTRW,U */
                  case 7: /* EXTRS = EXTRW,S */
! 		{
! 		    uint32_t pos = field(insn, 5, 5);
! 		    gen_movl_T0_im(pos);
! 		    gen_extrw(insn);
                      break;
! 		}
              }
              break;
          }
!             
          case 0x35: /* Deposit */
          {
--- 1602,1632 ----
              switch(ext3) {
                  case 0: /* VSHD = SHRPW with SAR */
!                     gen_movl_T0_cr(11);
!                     gen_shrpw(insn);
!                     break;
                  case 2: /* SHD = SHRPW */
!                 {
!                     uint32_t sa = 31 - field(insn, 5, 5);
!                     gen_movl_T0_im(sa);
!                     gen_shrpw(insn);
!                     break;
!                 }
                  case 4: /* VEXTRU = EXTRW,U with SAR */
                  case 5: /* VEXTRS = EXTRW,S with SAR */
!                     gen_movl_T0_cr(11);
!                     gen_extrw(insn);
!                     break;
                  case 6: /* EXTRU = EXTRW,U */
                  case 7: /* EXTRS = EXTRW,S */
!                 {
!                     uint32_t pos = field(insn, 5, 5);
!                     gen_movl_T0_im(pos);
!                     gen_extrw(insn);
                      break;
!                 }
              }
              break;
          }
! 
          case 0x35: /* Deposit */
          {
***************
*** 1636,1667 ****
                  case 0: /* VZDEP = DEPW,Z with SAR */
                  case 1: /* VDEP = DEPW with SAR */
! 		    gen_movl_T0_cr(11);
! 		    gen_depw(insn);
! 		    break;
                  case 2: /* ZDEP = DEPW,Z */
                  case 3: /* DEP = DEPW */
! 		{
! 		    uint32_t cpos = field(insn, 5, 5);
! 		    gen_movl_T0_im(cpos);
! 		    gen_depw(insn);
! 		    break;
! 		}
                  case 4: /* VZDEPI = DEPW,Z */
                  case 5: /* VDEPI = DEPW,Z */
! 		    gen_movl_T0_cr(11);
! 		    gen_depwi(insn);
! 		    break;
                  case 6: /* ZDEPI = DEPWI,Z */
                  case 7: /* DEPI = DEPWI */
! 		{
! 		    uint32_t cpos = field(insn, 5, 5);
! 		    gen_movl_T0_im(cpos);
! 		    gen_depwi(insn);
! 		    break;
! 		}
              }
              break;
          }
!         
          case 0x38: /* BE */
          case 0x39: /* BLE */
--- 1636,1667 ----
                  case 0: /* VZDEP = DEPW,Z with SAR */
                  case 1: /* VDEP = DEPW with SAR */
!                     gen_movl_T0_cr(11);
!                     gen_depw(insn);
!                     break;
                  case 2: /* ZDEP = DEPW,Z */
                  case 3: /* DEP = DEPW */
!                 {
!                     uint32_t cpos = field(insn, 5, 5);
!                     gen_movl_T0_im(cpos);
!                     gen_depw(insn);
!                     break;
!                 }
                  case 4: /* VZDEPI = DEPW,Z */
                  case 5: /* VDEPI = DEPW,Z */
!                     gen_movl_T0_cr(11);
!                     gen_depwi(insn);
!                     break;
                  case 6: /* ZDEPI = DEPWI,Z */
                  case 7: /* DEPI = DEPWI */
!                 {
!                     uint32_t cpos = field(insn, 5, 5);
!                     gen_movl_T0_im(cpos);
!                     gen_depwi(insn);
!                     break;
!                 }
              }
              break;
          }
! 
          case 0x38: /* BE */
          case 0x39: /* BLE */
***************
*** 1681,1685 ****
              break;
          }
!         
          case 0x3a: /* Branch */
          {
--- 1681,1685 ----
              break;
          }
! 
          case 0x3a: /* Branch */
          {
***************
*** 1712,1716 ****
              break;
          }
!         
          default: /* Illegal Instruction */
              gen_op_ill_insn();
--- 1712,1716 ----
              break;
          }
! 
          default: /* Illegal Instruction */
              gen_op_ill_insn();

Index: op.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v
retrieving revision 1.15
retrieving revision 1.16
diff -C2 -d -r1.15 -r1.16
*** op.c	12 Mar 2007 15:50:26 -0000	1.15
--- op.c	12 Mar 2007 15:54:19 -0000	1.16
***************
*** 269,283 ****
  void OPPROTO op_movl_T0_im(void)
  {
! 	T0 = PARAM1;
  }
  
  void OPPROTO op_movl_T1_im(void)
  {
! 	T1 = PARAM1;
  }
  
  void OPPROTO op_movl_T2_im(void)
  {
! 	T2 = PARAM1;
  }
  
--- 269,283 ----
  void OPPROTO op_movl_T0_im(void)
  {
!     T0 = PARAM1;
  }
  
  void OPPROTO op_movl_T1_im(void)
  {
!     T1 = PARAM1;
  }
  
  void OPPROTO op_movl_T2_im(void)
  {
!     T2 = PARAM1;
  }
  
***************
*** 440,444 ****
      tmp = T0;
      T0 += T1;
!     
      /* calculate carry flags */
      carry = (tmp & T1) | ((tmp | T1) & ~T0);
--- 440,444 ----
      tmp = T0;
      T0 += T1;
! 
      /* calculate carry flags */
      carry = (tmp & T1) | ((tmp | T1) & ~T0);
***************
*** 471,475 ****
      tmp = T0;
      T0 += T1;
!     
      /* add the carry */
      if (env->psw & PSW_CB7) {
--- 471,475 ----
      tmp = T0;
      T0 += T1;
! 
      /* add the carry */
      if (env->psw & PSW_CB7) {