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[HPPAQEMU-CVS] hppaqemu/target-hppa op.c, 1.11, 1.12 translate.c, 1.13, 1.14
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From: Randolph C. <ta...@us...> - 2007-03-11 16:11:44
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv1156/target-hppa Modified Files: op.c translate.c Log Message: redo the translation loop a bit start implementing some of the extract/deposit insns Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.13 retrieving revision 1.14 diff -C2 -d -r1.13 -r1.14 *** translate.c 11 Mar 2007 13:43:27 -0000 1.13 --- translate.c 11 Mar 2007 16:11:36 -0000 1.14 *************** *** 32,38 **** #define DEBUG_DISAS ! #define DYNAMIC_PC 1 /* dynamic pc value */ ! #define JUMP_PC 2 /* dynamic pc value which takes only two values ! according to jump_pc[T2] */ typedef struct DisasContext { --- 32,40 ---- #define DEBUG_DISAS ! #ifdef USE_DIRECT_JUMP ! #define TBPARAM(x) ! #else ! #define TBPARAM(x) (long)(x) ! #endif typedef struct DisasContext { *************** *** 40,44 **** target_ulong iasq[2]; unsigned int is_br:1; - unsigned int delay_slot_filled:1; struct TranslationBlock *tb; } DisasContext; --- 42,45 ---- *************** *** 476,482 **** }; ! static GenOpFunc1 *gen_op_movl_TN_im[2] = { gen_op_movl_T0_im, gen_op_movl_T1_im, }; --- 477,484 ---- }; ! static GenOpFunc1 *gen_op_movl_TN_im[3] = { gen_op_movl_T0_im, gen_op_movl_T1_im, + gen_op_movl_T2_im, }; *************** *** 496,499 **** --- 498,506 ---- } + static void gen_movl_T2_im(int val) + { + gen_movl_TN_im(2, val); + } + #define gen_op_ldst(name) gen_op_##name##_raw() *************** *** 606,615 **** target_ulong pc, target_ulong npc) { ! dc->is_br = 1; } static void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc) { ! gen_goto_tb(dc, 0, pc, npc); } --- 613,641 ---- target_ulong pc, target_ulong npc) { ! TranslationBlock *tb; ! tb = dc->tb; ! if ((tb->pc & TARGET_PAGE_MASK) == (pc & TARGET_PAGE_MASK)) { ! if (tb_num == 0) ! gen_op_goto_tb0(TBPARAM(tb)); ! else ! gen_op_goto_tb1(TBPARAM(tb)); ! gen_op_save_pc(pc, npc); ! gen_movl_T0_im((long)tb + tb_num); ! gen_op_exit_tb(); ! } else { ! gen_op_save_pc(pc, npc); ! gen_movl_T0_im(0); ! gen_op_exit_tb(); ! } } static void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc) { ! gen_goto_tb(dc, tb, pc, npc); ! } ! ! static void save_state(DisasContext *dc) ! { ! /* XXX */ } *************** *** 635,649 **** nb_gen_labels = 0; ! do { if (env->nb_breakpoints > 0) { for(j = 0; j < env->nb_breakpoints; j++) { if (env->breakpoints[j] == dc->iaoq[0]) { ! /* ! if (dc->iaoq[0] != pc_start) ! save_state(dc); gen_op_debug(); - gen_op_movl_T0_GR0(); - gen_op_exit_tb(); - */ dc->is_br = 1; goto exit_gen_loop; --- 661,671 ---- nb_gen_labels = 0; ! while (!dc->is_br && gen_opc_ptr < gen_opc_end) ! { if (env->nb_breakpoints > 0) { for(j = 0; j < env->nb_breakpoints; j++) { if (env->breakpoints[j] == dc->iaoq[0]) { ! save_state(dc); gen_op_debug(); dc->is_br = 1; goto exit_gen_loop; *************** *** 668,674 **** if (dc->is_br) break; - /* if the next PC is different, we abort now */ - if (dc->iaoq[0] != (last_pc + 4)) - break; /* if we reach a page boundary, we stop generation so that the PC of a TT_TFAULT exception is always in the right page */ --- 690,693 ---- *************** *** 677,705 **** /* if single step mode, we generate only one instruction and generate an exception */ ! if (env->singlestep_enabled) { ! gen_op_jmp_im(dc->iaoq[0]); ! gen_op_movl_T0_gr0(); ! gen_op_exit_tb(); ! break; ! } ! } while ((gen_opc_ptr < gen_opc_end) && ! (dc->iaoq[0] - pc_start) < (TARGET_PAGE_SIZE - 32)); exit_gen_loop: - if (!dc->is_br) { - if (dc->iaoq[0] != DYNAMIC_PC && - (dc->iaoq[1] != DYNAMIC_PC && dc->iaoq[1] != JUMP_PC)) { - /* static PC and NPC: we can use direct chaining */ - gen_branch(dc, (long)tb, dc->iaoq[0], dc->iaoq[1]); - } else { - if (dc->iaoq[0] != DYNAMIC_PC) - gen_op_jmp_im(dc->iaoq[0]); - /* - save_npc(dc); - gen_op_movl_T0_GR0(); - */ - gen_op_exit_tb(); - } - } *gen_opc_ptr = INDEX_op_end; if (search_pc) { --- 696,716 ---- /* if single step mode, we generate only one instruction and generate an exception */ ! if (env->singlestep_enabled) ! break; ! } ! if (env->singlestep_enabled) ! { ! save_state(dc); ! gen_op_debug(); ! goto exit_gen_loop; ! } ! else if (!dc->is_br) ! { ! save_state(dc); ! gen_goto_tb(dc, 0, dc->iaoq[0], dc->iaoq[1]); ! } ! gen_op_exit_tb(); exit_gen_loop: *gen_opc_ptr = INDEX_op_end; if (search_pc) { *************** *** 889,892 **** --- 900,955 ---- } + + static void gen_shrpw(uint32_t insn) + { + uint32_t r1 = field(insn, 16, 5); + uint32_t r2 = field(insn, 21, 5); + uint32_t t = field(insn, 0, 5); + + gen_movl_T1_reg(r1); + gen_movl_T2_reg(r2); + gen_op_shrpw_cc(); + gen_movl_reg_T0(t); + } + + static void gen_extrw(uint32_t insn) + { + uint32_t r = field(insn, 21, 5); + uint32_t t = field(insn, 16, 5); + uint32_t clen = 32 - field(insn, 0, 5); + int se = field(insn, 10, 1); + + gen_movl_T1_im(clen); + gen_movl_T2_reg(r); + gen_op_extrw_cc(); + gen_movl_reg_T0(t); + } + + static void gen_depw(uint32_t insn) + { + uint32_t t = field(insn, 21, 5); + uint32_t r = field(insn, 16, 5); + uint32_t clen = 32 - field(insn, 0, 5); + int nz = field(insn, 10, 1); + + gen_movl_T1_im(clen); + gen_movl_T2_reg(r); + gen_op_depw_cc(); + gen_movl_reg_T0(t); + } + + static void gen_depwi(uint32_t insn) + { + uint32_t t = field(insn, 21, 5); + uint32_t im5 = field_signext(insn, 16, 5); + uint32_t clen = 32 - field(insn, 0, 5); + int nz = field(insn, 10, 1); + + gen_movl_T1_im(clen); + gen_movl_T2_im(im5); + gen_op_depw_cc(); + gen_movl_reg_T0(t); + } + static void disas_hppa_insn(DisasContext * dc) { *************** *** 1530,1540 **** ext3 = field(insn, 10, 3); switch(ext3) { ! case 0: /* VSHD */ ! case 2: /* SHD */ ! case 4: /* VEXTRU */ ! case 5: /* VEXTRS */ ! case 6: /* EXTRU */ ! case 7: /* EXTRS */ break; } break; --- 1593,1620 ---- ext3 = field(insn, 10, 3); switch(ext3) { ! case 0: /* VSHD = SHRPW with SAR */ ! gen_movl_T0_cr(11); ! gen_shrpw(insn); ! break; ! case 2: /* SHD = SHRPW */ ! { ! uint32_t sa = 31 - field(insn, 5, 5); ! gen_movl_T0_im(sa); ! gen_shrpw(insn); ! break; ! } ! case 4: /* VEXTRU = EXTRW,U with SAR */ ! case 5: /* VEXTRS = EXTRW,S with SAR */ ! gen_movl_T0_cr(11); ! gen_extrw(insn); ! break; ! case 6: /* EXTRU = EXTRW,U */ ! case 7: /* EXTRS = EXTRW,S */ ! { ! uint32_t pos = field(insn, 5, 5); ! gen_movl_T0_im(pos); ! gen_extrw(insn); break; + } } break; *************** *** 1546,1558 **** ext3 = field(insn, 10, 3); switch(ext3) { ! case 0: /* VZDEP */ ! case 1: /* VDEP */ ! case 2: /* ZDEP */ ! case 3: /* DEP */ ! case 4: /* VZDEPI */ ! case 5: /* VDEPI */ ! case 6: /* ZDEPI */ ! case 7: /* DEPI */ ! break; } break; --- 1626,1655 ---- ext3 = field(insn, 10, 3); switch(ext3) { ! case 0: /* VZDEP = DEPW,Z with SAR */ ! case 1: /* VDEP = DEPW with SAR */ ! gen_movl_T0_cr(11); ! gen_depw(insn); ! break; ! case 2: /* ZDEP = DEPW,Z */ ! case 3: /* DEP = DEPW */ ! { ! uint32_t cpos = field(insn, 5, 5); ! gen_movl_T0_im(cpos); ! gen_depw(insn); ! break; ! } ! case 4: /* VZDEPI = DEPW,Z */ ! case 5: /* VDEPI = DEPW,Z */ ! gen_movl_T0_cr(11); ! gen_depwi(insn); ! break; ! case 6: /* ZDEPI = DEPWI,Z */ ! case 7: /* DEPI = DEPWI */ ! { ! uint32_t cpos = field(insn, 5, 5); ! gen_movl_T0_im(cpos); ! gen_depwi(insn); ! break; ! } } break; *************** *** 1590,1593 **** --- 1687,1691 ---- case 0: /* BL */ /* generate (iaoq_next <- iaoq_front + disp + 8) */ + gen_branch(dc, 0, dc->iaoq[0] + disp + 8, dc->iaoq[0] + disp + 12); /* generate (copy iaoq_back + 4 into t) */ /* if (n) generate (psw |= PSW_N); */ Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.11 retrieving revision 1.12 diff -C2 -d -r1.11 -r1.12 *** op.c 11 Mar 2007 13:43:26 -0000 1.11 --- op.c 11 Mar 2007 16:11:36 -0000 1.12 *************** *** 277,280 **** --- 277,285 ---- } + void OPPROTO op_movl_T2_im(void) + { + T2 = PARAM1; + } + #define OP_COPY(_t1, _t2) \ void OPPROTO op_copy_##_t1##_##_t2(void) \ *************** *** 318,321 **** --- 323,331 ---- } + void OPPROTO op_debug(void) + { + raise_exception(EXCP_DEBUG); + } + /* System operations */ void OPPROTO op_break(void) *************** *** 717,720 **** --- 727,767 ---- } + /* Shift/deposit insns */ + void OPPROTO op_shrpw_cc(void) + { + /* INPUT: T0 = shift amount, T1 and T2 = register pair values */ + /* OUTPUT: T0 */ + T0 &= 0x1f; + T0 = (T1 << (32 - T0)) | (T2 >> T0); + } + + void OPPROTO op_extrw_cc(void) + { + /* INPUT: T0 = shift pos, T1 = shift len, T2 = in value */ + /* OUTPUT: T0 */ + } + + void OPPROTO op_depw_cc(void) + { + /* INPUT: T0 = shift pos, T1 = shift len, T2 = in value */ + /* OUTPUT: T0 */ + } + + void OPPROTO op_save_pc(void) + { + env->iaoq[0] = PARAM1; + env->iaoq[1] = PARAM2; + } + + void OPPROTO op_goto_tb0(void) + { + GOTO_TB(op_goto_tb0, PARAM1, 0); + } + + void OPPROTO op_goto_tb1(void) + { + GOTO_TB(op_goto_tb1, PARAM1, 0); + } + void OPPROTO op_exit_tb(void) { |
