[HPPAQEMU-CVS] hppaqemu/target-hppa cpu.h, 1.4, 1.5 exec.h, 1.3, 1.4 helper.c, 1.2, 1.3 op.c, 1.6, 1.7 translate.c, 1.10, 1.11

[Randolph C. <ta...@us...>]

Update of /cvsroot/hppaqemu/hppaqemu/target-hppa
In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv17414/target-hppa

Modified Files:
	cpu.h exec.h helper.c op.c translate.c 
Log Message:
implement some insns


Index: translate.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -C2 -d -r1.10 -r1.11
*** translate.c	7 Mar 2007 05:27:31 -0000	1.10
--- translate.c	9 Mar 2007 15:57:31 -0000	1.11
***************
*** 221,224 ****
--- 221,412 ----
  };
  
+ static GenOpFunc *gen_op_movl_TN_cr[2][32] =
+ {
+     {
+         gen_op_movl_cr0_T0,
+         gen_op_movl_cr1_T0,
+         gen_op_movl_cr2_T0,
+         gen_op_movl_cr3_T0,
+         gen_op_movl_cr4_T0,
+         gen_op_movl_cr5_T0,
+         gen_op_movl_cr6_T0,
+         gen_op_movl_cr7_T0,
+         gen_op_movl_cr8_T0,
+         gen_op_movl_cr9_T0,
+         gen_op_movl_cr10_T0,
+         gen_op_movl_cr11_T0,
+         gen_op_movl_cr12_T0,
+         gen_op_movl_cr13_T0,
+         gen_op_movl_cr14_T0,
+         gen_op_movl_cr15_T0,
+         gen_op_movl_cr16_T0,
+         gen_op_movl_cr17_T0,
+         gen_op_movl_cr18_T0,
+         gen_op_movl_cr19_T0,
+         gen_op_movl_cr20_T0,
+         gen_op_movl_cr21_T0,
+         gen_op_movl_cr22_T0,
+         gen_op_movl_cr23_T0,
+         gen_op_movl_cr24_T0,
+         gen_op_movl_cr25_T0,
+         gen_op_movl_cr26_T0,
+         gen_op_movl_cr27_T0,
+         gen_op_movl_cr28_T0,
+         gen_op_movl_cr29_T0,
+         gen_op_movl_cr30_T0,
+         gen_op_movl_cr31_T0,
+     }, {
+         gen_op_movl_cr0_T1,
+         gen_op_movl_cr1_T1,
+         gen_op_movl_cr2_T1,
+         gen_op_movl_cr3_T1,
+         gen_op_movl_cr4_T1,
+         gen_op_movl_cr5_T1,
+         gen_op_movl_cr6_T1,
+         gen_op_movl_cr7_T1,
+         gen_op_movl_cr8_T1,
+         gen_op_movl_cr9_T1,
+         gen_op_movl_cr10_T1,
+         gen_op_movl_cr11_T1,
+         gen_op_movl_cr12_T1,
+         gen_op_movl_cr13_T1,
+         gen_op_movl_cr14_T1,
+         gen_op_movl_cr15_T1,
+         gen_op_movl_cr16_T1,
+         gen_op_movl_cr17_T1,
+         gen_op_movl_cr18_T1,
+         gen_op_movl_cr19_T1,
+         gen_op_movl_cr20_T1,
+         gen_op_movl_cr21_T1,
+         gen_op_movl_cr22_T1,
+         gen_op_movl_cr23_T1,
+         gen_op_movl_cr24_T1,
+         gen_op_movl_cr25_T1,
+         gen_op_movl_cr26_T1,
+         gen_op_movl_cr27_T1,
+         gen_op_movl_cr28_T1,
+         gen_op_movl_cr29_T1,
+         gen_op_movl_cr30_T1,
+         gen_op_movl_cr31_T1,
+     }
+ };
+ 
+ static GenOpFunc *gen_op_movl_cr_TN[2][32] =
+ {
+     {
+         gen_op_movl_T0_cr0,
+         gen_op_movl_T0_cr1,
+         gen_op_movl_T0_cr2,
+         gen_op_movl_T0_cr3,
+         gen_op_movl_T0_cr4,
+         gen_op_movl_T0_cr5,
+         gen_op_movl_T0_cr6,
+         gen_op_movl_T0_cr7,
+         gen_op_movl_T0_cr8,
+         gen_op_movl_T0_cr9,
+         gen_op_movl_T0_cr10,
+         gen_op_movl_T0_cr11,
+         gen_op_movl_T0_cr12,
+         gen_op_movl_T0_cr13,
+         gen_op_movl_T0_cr14,
+         gen_op_movl_T0_cr15,
+         gen_op_movl_T0_cr16,
+         gen_op_movl_T0_cr17,
+         gen_op_movl_T0_cr18,
+         gen_op_movl_T0_cr19,
+         gen_op_movl_T0_cr20,
+         gen_op_movl_T0_cr21,
+         gen_op_movl_T0_cr22,
+         gen_op_movl_T0_cr23,
+         gen_op_movl_T0_cr24,
+         gen_op_movl_T0_cr25,
+         gen_op_movl_T0_cr26,
+         gen_op_movl_T0_cr27,
+         gen_op_movl_T0_cr28,
+         gen_op_movl_T0_cr29,
+         gen_op_movl_T0_cr30,
+         gen_op_movl_T0_cr31,
+     }, {
+         gen_op_movl_T1_cr0,
+         gen_op_movl_T1_cr1,
+         gen_op_movl_T1_cr2,
+         gen_op_movl_T1_cr3,
+         gen_op_movl_T1_cr4,
+         gen_op_movl_T1_cr5,
+         gen_op_movl_T1_cr6,
+         gen_op_movl_T1_cr7,
+         gen_op_movl_T1_cr8,
+         gen_op_movl_T1_cr9,
+         gen_op_movl_T1_cr10,
+         gen_op_movl_T1_cr11,
+         gen_op_movl_T1_cr12,
+         gen_op_movl_T1_cr13,
+         gen_op_movl_T1_cr14,
+         gen_op_movl_T1_cr15,
+         gen_op_movl_T1_cr16,
+         gen_op_movl_T1_cr17,
+         gen_op_movl_T1_cr18,
+         gen_op_movl_T1_cr19,
+         gen_op_movl_T1_cr20,
+         gen_op_movl_T1_cr21,
+         gen_op_movl_T1_cr22,
+         gen_op_movl_T1_cr23,
+         gen_op_movl_T1_cr24,
+         gen_op_movl_T1_cr25,
+         gen_op_movl_T1_cr26,
+         gen_op_movl_T1_cr27,
+         gen_op_movl_T1_cr28,
+         gen_op_movl_T1_cr29,
+         gen_op_movl_T1_cr30,
+         gen_op_movl_T1_cr31,
+     }
+ };
+ 
+ static GenOpFunc *gen_op_movl_TN_sr[2][8] =
+ {
+     {
+         gen_op_movl_sr0_T0,
+         gen_op_movl_sr1_T0,
+         gen_op_movl_sr2_T0,
+         gen_op_movl_sr3_T0,
+         gen_op_movl_sr4_T0,
+         gen_op_movl_sr5_T0,
+         gen_op_movl_sr6_T0,
+         gen_op_movl_sr7_T0,
+     }, {
+         gen_op_movl_sr0_T1,
+         gen_op_movl_sr1_T1,
+         gen_op_movl_sr2_T1,
+         gen_op_movl_sr3_T1,
+         gen_op_movl_sr4_T1,
+         gen_op_movl_sr5_T1,
+         gen_op_movl_sr6_T1,
+         gen_op_movl_sr7_T1,
+     }
+ };
+ 
+ static GenOpFunc *gen_op_movl_sr_TN[2][32] =
+ {
+     {
+         gen_op_movl_T0_sr0,
+         gen_op_movl_T0_sr1,
+         gen_op_movl_T0_sr2,
+         gen_op_movl_T0_sr3,
+         gen_op_movl_T0_sr4,
+         gen_op_movl_T0_sr5,
+         gen_op_movl_T0_sr6,
+         gen_op_movl_T0_sr7,
+     }, {
+         gen_op_movl_T1_sr0,
+         gen_op_movl_T1_sr1,
+         gen_op_movl_T1_sr2,
+         gen_op_movl_T1_sr3,
+         gen_op_movl_T1_sr4,
+         gen_op_movl_T1_sr5,
+         gen_op_movl_T1_sr6,
+         gen_op_movl_T1_sr7,
+     }
+ };
+ 
  static GenOpFunc1 *gen_op_movl_TN_im[2] = {
      gen_op_movl_T0_im,
***************
*** 243,252 ****
  }
  
  static void gen_movl_reg_TN(int reg, int t)
  {
!     if (reg)
!         gen_op_movl_reg_TN[t][reg] ();
!     else
!         gen_movl_imm_TN(t, 0);
  }
  
--- 431,438 ----
  }
  
+ /* General registers */
  static void gen_movl_reg_TN(int reg, int t)
  {
!     gen_op_movl_reg_TN[t][reg] ();
  }
  
***************
*** 263,268 ****
  static void gen_movl_TN_reg(int reg, int t)
  {
!     if (reg)
!         gen_op_movl_TN_reg[t][reg] ();
  }
  
--- 449,453 ----
  static void gen_movl_TN_reg(int reg, int t)
  {
!     gen_op_movl_TN_reg[t][reg] ();
  }
  
***************
*** 277,281 ****
  }
  
! #define gen_op_shift_T0(s) gen_op_shift##s##_T0()
  
  static void gen_goto_tb(DisasContext *dc, int tb_num, 
--- 462,509 ----
  }
  
! /* Control registers */
! static void gen_movl_cr_T0(int cr)
! {
!     gen_op_movl_cr_TN[0][cr]();
! }
! 
! static void gen_movl_cr_T1(int cr)
! {
!     gen_op_movl_cr_TN[1][cr]();
! }
! 
! static void gen_movl_T0_cr(int cr)
! {
!     gen_op_movl_TN_cr[0][cr]();
! }
! 
! static void gen_movl_T1_cr(int cr)
! {
!     gen_op_movl_TN_cr[1][cr]();
! }
! 
! /* Space registers */
! static void gen_movl_sr_T0(int sr)
! {
!     gen_op_movl_sr_TN[0][sr]();
! }
! 
! static void gen_movl_sr_T1(int sr)
! {
!     gen_op_movl_sr_TN[1][sr]();
! }
! 
! static void gen_movl_T0_sr(int sr)
! {
!     gen_op_movl_TN_sr[0][sr]();
! }
! 
! static void gen_movl_T1_sr(int sr)
! {
!     gen_op_movl_TN_sr[1][sr]();
! }
! 
! #define gen_shift_T0(s) gen_op_shift##s##_T0()
! #define gen_shift_T1(s) gen_op_shift##s##_T1()
  
  static void gen_goto_tb(DisasContext *dc, int tb_num, 
***************
*** 355,359 ****
          if (env->singlestep_enabled) {
              gen_op_jmp_im(dc->iaoq[0]);
!             gen_op_movl_T0_GR0();
              gen_op_exit_tb();
              break;
--- 583,587 ----
          if (env->singlestep_enabled) {
              gen_op_jmp_im(dc->iaoq[0]);
!             gen_op_movl_T0_gr0();
              gen_op_exit_tb();
              break;
***************
*** 460,473 ****
--- 688,754 ----
              switch(ext8) {
                  case 0x00: /* BREAK */
+ 		    gen_op_break();
+ 		    break;
+ 
                  case 0x20: /* SYNC, SYNCDMAA */
+ 		    if (field(insn, 20, 1))
+ 		        gen_op_syncdma();
+                     else
+ 		        gen_op_sync();
+ 		    break;
+ 
                  case 0x60: /* RFI */
+                     gen_op_rfi();
+                     dc->is_br = 1;
+                     break;
+ 
                  case 0x65: /* RFIR */
+                     gen_op_rfi();
+                     gen_op_restore_shadow();
+                     dc->is_br = 1;
+                     break;
+ 
                  case 0x6b: /* SSM */
+                     gen_op_ssm(field(insn, 16, 7));
+                     gen_movl_reg_T0(field(insn, 0, 5));
+                     break;
+                    
                  case 0x73: /* RSM */
+                     gen_op_rsm(field(insn, 16, 7));
+                     gen_movl_reg_T0(field(insn, 0, 5));
+                     break;
+ 
                  case 0xc3: /* MTSM */
+                     gen_movl_T0_reg(field(insn, 16, 5));
+                     gen_op_mtsm();
+                     break;
+ 
                  case 0x85: /* LDSID */
+                 {
+                     uint32_t s, b, t;
+                     s = field(insn, 14, 2);
+                     b = field(insn, 21, 5);
+                     t = field(insn, 0, 5);
+                     break;
+                 }
+ 
                  case 0xc1: /* MTSP */
+                 {
+                     uint32_t sr = field(insn, 13, 3);
+                     uint32_t r = field(insn, 16, 5);
+                     gen_movl_T0_reg(r);
+                     gen_movl_sr_T0(sr);
+                     break;
+                 }
                  case 0x25: /* MFSP */
+                 {
+                     uint32_t sr = field(insn, 13, 3);
+                     uint32_t t = field(insn, 0, 5);
+                     gen_movl_T0_sr(sr);
+                     gen_movl_reg_T0(t);
+                     break;
+                 }
                  case 0xc2: /* MTCTL */
+                 
                  case 0x45: /* MFCTL */
                      break;
***************
*** 559,583 ****
                      break;
                  case 0x19: /* SH1ADD */
!                     gen_op_shift_T0(1);
                      gen_op_add_T1_T0();
                      break;
                  case 0x39: /* SH1ADDO */
!                     gen_op_shift_T0(1);
                      gen_op_addo_T1_T0();
                      break;
                  case 0x1a: /* SH2ADD */
!                     gen_op_shift_T0(2);
                      gen_op_add_T1_T0();
                      break;
                  case 0x3a: /* SH2ADDO */
!                     gen_op_shift_T0(2);
                      gen_op_addo_T1_T0();
                      break;
                  case 0x1b: /* SH3ADD */
!                     gen_op_shift_T0(3);
                      gen_op_add_T1_T0();
                      break;
                  case 0x3b: /* SH3ADDO */
!                     gen_op_shift_T0(3);
                      gen_op_addo_T1_T0();
                      break;
--- 840,864 ----
                      break;
                  case 0x19: /* SH1ADD */
!                     gen_shift_T0(1);
                      gen_op_add_T1_T0();
                      break;
                  case 0x39: /* SH1ADDO */
!                     gen_shift_T0(1);
                      gen_op_addo_T1_T0();
                      break;
                  case 0x1a: /* SH2ADD */
!                     gen_shift_T0(2);
                      gen_op_add_T1_T0();
                      break;
                  case 0x3a: /* SH2ADDO */
!                     gen_shift_T0(2);
                      gen_op_addo_T1_T0();
                      break;
                  case 0x1b: /* SH3ADD */
!                     gen_shift_T0(3);
                      gen_op_add_T1_T0();
                      break;
                  case 0x3b: /* SH3ADDO */
!                     gen_shift_T0(3);
                      gen_op_addo_T1_T0();
                      break;
***************
*** 632,644 ****
                      break;
                  case 0x29: /* SH1ADDL */
!                     gen_op_shift_T0(1);
                      gen_op_addl_T1_T0();
                      break;
                  case 0x2A: /* SH2ADDL */
!                     gen_op_shift_T0(2);
                      gen_op_addl_T1_T0();
                      break;
                  case 0x2B: /* SH3ADDL */
!                     gen_op_shift_T0(3);
                      gen_op_addl_T1_T0();
                      break;
--- 913,925 ----
                      break;
                  case 0x29: /* SH1ADDL */
!                     gen_shift_T0(1);
                      gen_op_addl_T1_T0();
                      break;
                  case 0x2A: /* SH2ADDL */
!                     gen_shift_T0(2);
                      gen_op_addl_T1_T0();
                      break;
                  case 0x2B: /* SH3ADDL */
!                     gen_shift_T0(3);
                      gen_op_addl_T1_T0();
                      break;

Index: helper.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/helper.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** helper.c	6 Mar 2007 14:41:50 -0000	1.2
--- helper.c	9 Mar 2007 15:57:31 -0000	1.3
***************
*** 1,8 ****
! #include <stdio.h>
! #include <stdlib.h>
! #include <string.h>
  
! #include "cpu.h"
! #include "exec-all.h"
  
  int cpu_hppa_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
--- 1,17 ----
! #include "exec.h"
  
! void raise_exception(int tt)
! {
!     env->cr[18] = env->iaoq[0];
!     env->iiaoq_back = env->iaoq[1];
!     env->cr[17] = env->iasq[0];
!     env->iiasq_back = env->iasq[1];
!     env->cr[19] = ldl_code(env->iaoq[0]);
!     env->cr[20] = 0; /* isr */
!     env->cr[21] = 0; /* ior */
!     env->cr[22] = env->psw;
!     env->exception_index = tt;
!     cpu_loop_exit();
! }
  
  int cpu_hppa_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

Index: exec.h
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/exec.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** exec.h	4 Mar 2007 15:16:27 -0000	1.3
--- exec.h	9 Mar 2007 15:57:31 -0000	1.4
***************
*** 42,44 ****
--- 42,47 ----
  }
  
+ void raise_exception(int tt);
+ void cpu_loop_exit(void);
+ 
  #endif

Index: op.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** op.c	6 Mar 2007 14:41:50 -0000	1.6
--- op.c	9 Mar 2007 15:57:31 -0000	1.7
***************
*** 21,27 ****
  #include "exec.h"
  
! #define REGNAME gr0
! #define REG (env->gr[0])
! #include "op_template.h"
  #define REGNAME gr1
  #define REG (env->gr[1])
--- 21,25 ----
  #include "exec.h"
  
! /* General registers */
  #define REGNAME gr1
  #define REG (env->gr[1])
***************
*** 118,136 ****
  #include "op_template.h"
  
! void OPPROTO op_movl_T0_GR0(void)
  {
  	T0 = 0;
  }
  
! void OPPROTO op_movl_T1_GR0(void)
  {
  	T1 = 0;
  }
  
! void OPPROTO op_movl_GR0_T0(void)
  {
  }
  
! void OPPROTO op_movl_GR0_T1(void)
  {
  }
--- 116,258 ----
  #include "op_template.h"
  
! /* Space registers */
! #define REGNAME sr0
! #define REG (env->sr[0])
! #include "op_template.h"
! #define REGNAME sr1
! #define REG (env->sr[1])
! #include "op_template.h"
! #define REGNAME sr2
! #define REG (env->sr[2])
! #include "op_template.h"
! #define REGNAME sr3
! #define REG (env->sr[3])
! #include "op_template.h"
! #define REGNAME sr4
! #define REG (env->sr[4])
! #include "op_template.h"
! #define REGNAME sr5
! #define REG (env->sr[5])
! #include "op_template.h"
! #define REGNAME sr6
! #define REG (env->sr[6])
! #include "op_template.h"
! #define REGNAME sr7
! #define REG (env->sr[7])
! #include "op_template.h"
! 
! /* Control registers */
! #define REGNAME cr0
! #define REG (env->cr[0])
! #include "op_template.h"
! #define REGNAME cr1
! #define REG (env->cr[1])
! #include "op_template.h"
! #define REGNAME cr2
! #define REG (env->cr[2])
! #include "op_template.h"
! #define REGNAME cr3
! #define REG (env->cr[3])
! #include "op_template.h"
! #define REGNAME cr4
! #define REG (env->cr[4])
! #include "op_template.h"
! #define REGNAME cr5
! #define REG (env->cr[5])
! #include "op_template.h"
! #define REGNAME cr6
! #define REG (env->cr[6])
! #include "op_template.h"
! #define REGNAME cr7
! #define REG (env->cr[7])
! #include "op_template.h"
! #define REGNAME cr8
! #define REG (env->cr[8])
! #include "op_template.h"
! #define REGNAME cr9
! #define REG (env->cr[9])
! #include "op_template.h"
! #define REGNAME cr10
! #define REG (env->cr[10])
! #include "op_template.h"
! #define REGNAME cr11
! #define REG (env->cr[11])
! #include "op_template.h"
! #define REGNAME cr12
! #define REG (env->cr[12])
! #include "op_template.h"
! #define REGNAME cr13
! #define REG (env->cr[13])
! #include "op_template.h"
! #define REGNAME cr14
! #define REG (env->cr[14])
! #include "op_template.h"
! #define REGNAME cr15
! #define REG (env->cr[15])
! #include "op_template.h"
! #define REGNAME cr16
! #define REG (env->cr[16])
! #include "op_template.h"
! #define REGNAME cr17
! #define REG (env->cr[17])
! #include "op_template.h"
! #define REGNAME cr18
! #define REG (env->cr[18])
! #include "op_template.h"
! #define REGNAME cr19
! #define REG (env->cr[19])
! #include "op_template.h"
! #define REGNAME cr20
! #define REG (env->cr[20])
! #include "op_template.h"
! #define REGNAME cr21
! #define REG (env->cr[21])
! #include "op_template.h"
! #define REGNAME cr22
! #define REG (env->cr[22])
! #include "op_template.h"
! #define REGNAME cr23
! #define REG (env->cr[23])
! #include "op_template.h"
! #define REGNAME cr24
! #define REG (env->cr[24])
! #include "op_template.h"
! #define REGNAME cr25
! #define REG (env->cr[25])
! #include "op_template.h"
! #define REGNAME cr26
! #define REG (env->cr[26])
! #include "op_template.h"
! #define REGNAME cr27
! #define REG (env->cr[27])
! #include "op_template.h"
! #define REGNAME cr28
! #define REG (env->cr[28])
! #include "op_template.h"
! #define REGNAME cr29
! #define REG (env->cr[29])
! #include "op_template.h"
! #define REGNAME cr30
! #define REG (env->cr[30])
! #include "op_template.h"
! #define REGNAME cr31
! #define REG (env->cr[31])
! #include "op_template.h"
! 
! void OPPROTO op_movl_T0_gr0(void)
  {
  	T0 = 0;
  }
  
! void OPPROTO op_movl_T1_gr0(void)
  {
  	T1 = 0;
  }
  
! void OPPROTO op_movl_gr0_T0(void)
  {
  }
  
! void OPPROTO op_movl_gr0_T1(void)
  {
  }
***************
*** 146,149 ****
--- 268,369 ----
  }
  
+ /* System operations */
+ void OPPROTO op_break(void)
+ {
+     raise_exception(EXCP_BREAK);
+ }
+ 
+ void OPPROTO op_sync(void)
+ {
+ }
+ 
+ void OPPROTO op_syncdma(void)
+ {
+ }
+ 
+ void OPPROTO op_rfi(void)
+ {
+     if (env->priv_level != 0)
+         raise_exception(EXCP_PRIVOP);
+     else {
+         env->psw = env->cr[22]; /* ipsw */
+         env->iaoq[0] = env->cr[18]; /* iiaoq */
+         env->iaoq[1] = env->iiaoq_back;
+         env->iasq[0] = env->cr[17]; /* iiasq */
+         env->iasq[1] = env->iiasq_back;
+     }
+ }
+ 
+ void OPPROTO op_restore_shadow(void)
+ {
+     /* restore shadow registers */
+     env->gr[1] = env->shr[0];
+     env->gr[8] = env->shr[1];
+     env->gr[9] = env->shr[2];
+     env->gr[16] = env->shr[3];
+     env->gr[17] = env->shr[4];
+     env->gr[24] = env->shr[5];
+     env->gr[25] = env->shr[6];
+ }
+ 
+ void OPPROTO op_ssm(void)
+ {
+     if (env->priv_level != 0)
+         raise_exception(EXCP_PRIVOP);
+     T0 = env->psw & (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I);
+ 
+     if (PARAM1 & (1 << 0))
+       env->psw |= PSW_W;
+     if (PARAM1 & (1 << 1))
+       env->psw |= PSW_E;
+     if (PARAM1 & (1 << 2))
+       env->psw |= PSW_O;
+     if (PARAM1 & (1 << 3))
+       env->psw |= PSW_G;
+     if (PARAM1 & (1 << 4))
+       env->psw |= PSW_F;
+     if (PARAM1 & (1 << 5))
+       env->psw |= PSW_R;
+     if (PARAM1 & (1 << 7))
+       env->psw |= PSW_P;
+     if (PARAM1 & (1 << 8))
+       env->psw |= PSW_D;
+     if (PARAM1 & (1 << 9))
+       env->psw |= PSW_I;
+ }
+ 
+ void OPPROTO op_rsm(void)
+ {
+     if (env->priv_level != 0)
+         raise_exception(EXCP_PRIVOP);
+     T0 = env->psw & (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I);
+ 
+     if (PARAM1 & (1 << 0))
+       env->psw &= ~PSW_W;
+     if (PARAM1 & (1 << 1))
+       env->psw &= ~PSW_E;
+     if (PARAM1 & (1 << 2))
+       env->psw &= ~PSW_O;
+     if (PARAM1 & (1 << 3))
+       env->psw &= ~PSW_G;
+     if (PARAM1 & (1 << 4))
+       env->psw &= ~PSW_F;
+     if (PARAM1 & (1 << 5))
+       env->psw &= ~PSW_R;
+     if (PARAM1 & (1 << 7))
+       env->psw &= ~PSW_P;
+     if (PARAM1 & (1 << 8))
+       env->psw &= ~PSW_D;
+     if (PARAM1 & (1 << 9))
+       env->psw &= ~PSW_I;
+ }
+ 
+ void OPPROTO op_mtsm(void)
+ {
+     if (env->priv_level != 0)
+         raise_exception(EXCP_PRIVOP);
+     env->psw = env->psw & ~(PSW_W | PSW_E | PSW_O | PSW_G | PSW_F | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I);
+     env->psw |= T0 & (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I);
+ }
  
  /* computation instructions... page 169 PA1.1 specification */

Index: cpu.h
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/cpu.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** cpu.h	6 Mar 2007 14:41:50 -0000	1.4
--- cpu.h	9 Mar 2007 15:57:31 -0000	1.5
***************
*** 101,105 ****
  #define PSW_I   0x80000000
  
! #define PSW_CB7_SHIFT	7	/* CHECK */
  
  typedef struct CPUHPPAState {
--- 101,105 ----
  #define PSW_I   0x80000000
  
! #define PSW_CB7_SHIFT	8	/* CHECK */
  
  typedef struct CPUHPPAState {
***************
*** 116,119 ****
--- 116,123 ----
      target_ulong iaoq[2]; /* Instruction Address Offset Queue */
      uint32_t iasq[2];     /* Instruction Address Space Queue */
+     target_ulong iiaoq_back;
+     uint32_t iiasq_back;
+ 
+     uint8_t priv_level;
  
   /*  gr[0]  : permanently 0