[HPPAQEMU-CVS] hppaqemu/target-hppa cpu.h, 1.3, 1.4 helper.c, 1.1, 1.2 op.c, 1.5, 1.6 translate.c,

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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa
In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv8436/target-hppa

Modified Files:
	cpu.h helper.c op.c translate.c 
Log Message:
fill in cpu_loop so that it will start running code
fill in gen_intermediate_code to fill in translation blocks
add link script to link qemu-hppa properly
turn on hppa in_asm decoding


Index: translate.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** translate.c	5 Mar 2007 14:32:27 -0000	1.8
--- translate.c	6 Mar 2007 14:41:50 -0000	1.9
***************
*** 30,36 ****
--- 30,43 ----
  #include "disas.h"
  
+ #define DEBUG_DISAS
+ 
+ #define DYNAMIC_PC  1 /* dynamic pc value */
+ #define JUMP_PC     2 /* dynamic pc value which takes only two values
+                          according to jump_pc[T2] */
+ 
  typedef struct DisasContext {
      target_ulong iaoq[2];
      target_ulong iasq[2];
+     int is_br;
      struct TranslationBlock *tb;
  } DisasContext;
***************
*** 49,52 ****
--- 56,61 ----
  #include "gen-op.h"
  
+ static void disas_hppa_insn(DisasContext * dc);
+ 
  static inline uint32_t field(uint32_t val, int start, int length) {
      val >>= start;
***************
*** 270,278 ****
  #define gen_op_shift_T0(s) gen_op_shift##s##_T0()
  
  static inline int gen_intermediate_code_internal(CPUState *env, 
                                                   TranslationBlock *tb, 
                                                   int search_pc)
  {
!     return -1;
  }
  
--- 279,412 ----
  #define gen_op_shift_T0(s) gen_op_shift##s##_T0()
  
+ static inline void gen_goto_tb(DisasContext *s, int tb_num, 
+                                target_ulong pc, target_ulong npc)
+ {
+ }
+ 
+ static inline void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc)
+ {
+     gen_goto_tb(dc, 0, pc, npc);
+ }
+ 
  static inline int gen_intermediate_code_internal(CPUState *env, 
                                                   TranslationBlock *tb, 
                                                   int search_pc)
  {
!     target_ulong pc_start, last_pc;
!     uint16_t *gen_opc_end;
!     DisasContext dc1, *dc = &dc1;
!     int j, lj = -1;
! 
!     memset(dc, 0, sizeof(DisasContext));
!     dc->tb = tb;
!     pc_start = tb->pc;
!     dc->iaoq[0] = pc_start;
!     last_pc = dc->iaoq[0];
!     dc->iaoq[1] = (target_ulong) tb->cs_base; /* CHECK */
!     gen_opc_ptr = gen_opc_buf;
!     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
!     gen_opparam_ptr = gen_opparam_buf;
!     nb_gen_labels = 0;
! 
!     do {
!         if (env->nb_breakpoints > 0) {
!             for(j = 0; j < env->nb_breakpoints; j++) {
!                 if (env->breakpoints[j] == dc->iaoq[0]) {
! 		    /*
! 		    if (dc->iaoq[0] != pc_start)
! 			save_state(dc);
!                     gen_op_debug();
! 		    gen_op_movl_T0_GR0();
! 		    gen_op_exit_tb();
! 		    */
! 		    dc->is_br = 1;
!                     goto exit_gen_loop;
!                 }
!             }
!         }
!         if (search_pc) {
!             if (loglevel > 0)
!                 fprintf(logfile, "Search PC...\n");
!             j = gen_opc_ptr - gen_opc_buf;
!             if (lj < j) {
!                 lj++;
!                 while (lj < j)
!                     gen_opc_instr_start[lj++] = 0;
!                 gen_opc_pc[lj] = dc->iaoq[0];
!                 gen_opc_instr_start[lj] = 1;
!             }
!         }
! 	last_pc = dc->iaoq[0];
! 	disas_hppa_insn(dc);
! 
! 	if (dc->is_br)
! 	    break;
! 	/* if the next PC is different, we abort now */
! 	if (dc->iaoq[0] != (last_pc + 4))
! 	    break;
!         /* if we reach a page boundary, we stop generation so that the
!            PC of a TT_TFAULT exception is always in the right page */
!         if ((dc->iaoq[0] & (TARGET_PAGE_SIZE - 1)) == 0)
!             break;
!         /* if single step mode, we generate only one instruction and
!            generate an exception */
!         if (env->singlestep_enabled) {
!             gen_op_jmp_im(dc->iaoq[0]);
!             gen_op_movl_T0_GR0();
!             gen_op_exit_tb();
!             break;
!         }
!     } while ((gen_opc_ptr < gen_opc_end) &&
! 	     (dc->iaoq[0] - pc_start) < (TARGET_PAGE_SIZE - 32));
! 
!  exit_gen_loop:
!     if (!dc->is_br) {
!         if (dc->iaoq[0] != DYNAMIC_PC && 
!             (dc->iaoq[1] != DYNAMIC_PC && dc->iaoq[1] != JUMP_PC)) {
!             /* static PC and NPC: we can use direct chaining */
!             gen_branch(dc, (long)tb, dc->iaoq[0], dc->iaoq[1]);
!         } else {
!             if (dc->iaoq[0] != DYNAMIC_PC)
!                 gen_op_jmp_im(dc->iaoq[0]);
! 	    /*
!             save_npc(dc);
!             gen_op_movl_T0_GR0();
! 	    */
!             gen_op_exit_tb();
!         }
!     }
!     *gen_opc_ptr = INDEX_op_end;
!     if (search_pc) {
!         j = gen_opc_ptr - gen_opc_buf;
!         lj++;
!         while (lj <= j)
!             gen_opc_instr_start[lj++] = 0;
!         tb->size = 0;
! #if 0
!         if (loglevel > 0) {
!             page_dump(logfile);
!         }
! #endif
! /*
!         gen_opc_jump_pc[0] = dc->jump_pc[0];
!         gen_opc_jump_pc[1] = dc->jump_pc[1];
! */
!     } else {
!         tb->size = last_pc + 4 - pc_start;
!     }
! #ifdef DEBUG_DISAS
!     if (loglevel & CPU_LOG_TB_IN_ASM) {
! 	fprintf(logfile, "--------------\n");
! 	fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
! 	target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
! 	fprintf(logfile, "\n");
!         if (loglevel & CPU_LOG_TB_OP) {
!             fprintf(logfile, "OP:\n");
!             dump_ops(gen_opc_buf, gen_opparam_buf);
!             fprintf(logfile, "\n");
!         }
!     }
! #endif
!     return 0;
  }
  

Index: helper.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/helper.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** helper.c	4 Mar 2007 23:19:41 -0000	1.1
--- helper.c	6 Mar 2007 14:41:50 -0000	1.2
***************
*** 18,19 ****
--- 18,29 ----
  
  
+ #if defined (CONFIG_USER_ONLY)
+ void do_interrupt (CPUState *env)
+ {
+     env->exception_index = -1;
+ }
+ #else
+ void do_interrupt (CPUState *env)
+ {
+ }
+ #endif /* !CONFIG_USER_ONLY */

Index: op.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** op.c	5 Mar 2007 14:32:27 -0000	1.5
--- op.c	6 Mar 2007 14:41:50 -0000	1.6
***************
*** 395,397 ****
--- 395,408 ----
  }
  
+ void OPPROTO op_exit_tb(void)
+ {
+     EXIT_TB();
+ }
+ 
+ void OPPROTO op_jmp_im(void)
+ {
+     env->iaoq[0] = (uint32_t)PARAM1;
+     env->iaoq[1] = env->iaoq[0] + 4;
+ }
+ 
  #include "op_mem.h"

Index: cpu.h
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/cpu.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** cpu.h	4 Mar 2007 15:16:27 -0000	1.3
--- cpu.h	6 Mar 2007 14:41:50 -0000	1.4
***************
*** 33,36 ****
--- 33,69 ----
  #define ELF_MACHINE	EM_PARISC
  
+ /* Group 1 interruptions */
+ #define EXCP_HPMC	1	/* High-priority machine check */
+ /* Group 2 interruptions */
+ #define EXCP_POWERFAIL	2
+ #define EXCP_RCVRCTR	3
+ #define EXCP_EXTINT	4
+ #define EXCP_LPMC	5
+ #define EXCP_PERFMON	29
+ /* Group 3 interruptions */
+ #define EXCP_ITLBMISS	6
+ #define EXCP_IMEMTRAP	7
+ #define EXCP_ILLEGAL	8
+ #define EXCP_BREAK	9
+ #define EXCP_PRIVOP	10
+ #define EXCP_PRIVREG	11
+ #define EXCP_OVERFLOW	12
+ #define EXCP_CONDITIONAL 13
+ #define EXCP_ASSISTEX	14
+ #define EXCP_DTLBMISS	15
+ #define EXCP_NAITLBMISS	16
+ #define EXCP_NADTLBMISS	17
+ #define EXCP_DMEMACCESS	26
+ #define EXCP_DMEMPROT	27
+ #define EXCP_UNALIGNED	28
+ #define EXCP_DMEMPROT2	19
+ #define EXCP_TLBDIRTY	20
+ #define EXCP_PAGEREF	21
+ #define EXCP_ASSISTEMU	22
+ /* Group 4 interruptions */
+ #define EXCP_HIPRIVXFER	23
+ #define EXCP_LOPRIVXFER	24
+ #define EXCP_TAKENBR	25
+ 
  /* the shadow registers map to the following general registers */
  // int shrmap[] = { 1, 6, 9, 16, 17, 24, 25 };

[HPPAQEMU-CVS] hppaqemu/target-hppa cpu.h, 1.3, 1.4 helper.c, 1.1, 1.2 op.c, 1.5, 1.6 translate.c,

[HPPAQEMU-CVS] hppaqemu/target-hppa cpu.h, 1.3, 1.4 helper.c, 1.1, 1.2 op.c, 1.5, 1.6 translate.c, 1.8, 1.9