[HPPAQEMU-CVS] hppaqemu/target-hppa cpu.h, 1.2, 1.3 exec.h, 1.2, 1.3 op.c, 1.3, 1.4 translate.c, 1.3, 1.4

[Randolph C. <ta...@us...>]

Update of /cvsroot/hppaqemu/hppaqemu/target-hppa
In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv12958/target-hppa

Modified Files:
	cpu.h exec.h op.c translate.c 
Log Message:
beginning of hppa target support


Index: translate.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** translate.c	2 Mar 2007 23:47:46 -0000	1.3
--- translate.c	4 Mar 2007 15:16:27 -0000	1.4
***************
*** 20,23 ****
--- 20,28 ----
   * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
   */
+ #include <stdarg.h>
+ #include <stdlib.h>
+ #include <stdio.h>
+ #include <string.h>
+ #include <inttypes.h>
  
  #include "cpu.h"
***************
*** 31,34 ****
--- 36,52 ----
  } DisasContext;
  
+ static uint16_t *gen_opc_ptr;
+ static uint32_t *gen_opparam_ptr;
+ extern FILE *logfile;
+ extern int loglevel;
+ 
+ enum {
+ #define DEF(s,n,copy_size) INDEX_op_ ## s,
+ #include "opc.h"
+ #undef DEF
+     NB_OPS
+ };
+ #include "gen-op.h"
+ 
  static inline uint32_t field(uint32_t val, int start, int length) {
      val >>= start;
***************
*** 208,217 ****
  static inline void gen_movl_imm_T0(int val)
  {
!     gen_movl_imm_T0(0, val);
  }
  
  static inline void gen_movl_imm_T1(int val)
  {
!     gen_movl_imm_T1(1, val);
  }
  
--- 226,235 ----
  static inline void gen_movl_imm_T0(int val)
  {
!     gen_movl_imm_TN(0, val);
  }
  
  static inline void gen_movl_imm_T1(int val)
  {
!     gen_movl_imm_TN(1, val);
  }
  
***************
*** 314,318 ****
                  uint32_t ext7;
                  ext7 = field(insn, 6, 7);
!                 swtich(ext7)
                  {
                      case 0x01: /* IITLBA */
--- 332,336 ----
                  uint32_t ext7;
                  ext7 = field(insn, 6, 7);
!                 switch(ext7)
                  {
                      case 0x01: /* IITLBA */
***************
*** 329,334 ****
                  }
              } else {
!                 uint32_t ext7;
                  ext8 = field(insn, 6, 8);
                  {
                      case 0x40: /* IDTLBP */
--- 347,354 ----
                  }
              } else {
!                 uint32_t ext8;
                  ext8 = field(insn, 6, 8);
+ 
+ 		switch (ext8)
                  {
                      case 0x40: /* IDTLBP */
***************
*** 632,636 ****
          case 0x1a: /* STW */
          {
!             uint32_t b, r, s, im14;
              b = field(insn, 21, 5);
              t = field(insn, 16, 5);
--- 652,656 ----
          case 0x1a: /* STW */
          {
!             uint32_t b, t, r, s, im14;
              b = field(insn, 21, 5);
              t = field(insn, 16, 5);
***************
*** 685,688 ****
--- 705,709 ----
          case 0x25: /* SUBI, SUBIO */
          {
+             uint32_t r, t, im11;
              r = field(insn, 21, 5);
              t = field(insn, 16, 5);
***************
*** 760,764 ****
          case 0x39: /* BLE */
          {
!             uint32_t b, w1, s, w2, n, w;
              b = field(insn, 21, 5);
              w1 = field_signext(insn, 16, 5);
--- 781,785 ----
          case 0x39: /* BLE */
          {
!             uint32_t b, w1, s, w2, n, w, disp;
              b = field(insn, 21, 5);
              w1 = field_signext(insn, 16, 5);
***************
*** 774,778 ****
          case 0x3a: /* Branch */
          {
!             uint32_t t, w1, ext3, w2, n, disp;
              ext3 = field(insn, 13, 3);
              t = field(insn, 21, 5);
--- 795,799 ----
          case 0x3a: /* Branch */
          {
!             uint32_t t, w, w1, ext3, w2, n, disp;
              ext3 = field(insn, 13, 3);
              t = field(insn, 21, 5);
***************
*** 802,803 ****
--- 823,864 ----
      }
  }
+ 
+ CPUHPPAState *cpu_hppa_init(void)
+ {
+     CPUHPPAState *env;
+ 
+     env = qemu_mallocz(sizeof(CPUHPPAState));
+     if (!env)
+ 	return NULL;
+     cpu_exec_init(env);
+     tlb_flush(env, 1);
+     return env;
+ }
+ 
+ void cpu_dump_state(CPUState *env, FILE *f, 
+                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
+                     int flags)
+ {
+     int i;
+ 
+     cpu_fprintf(f, "PSW = %08X\n", env->psw);
+     for(i=0;i<31;i++) {
+         cpu_fprintf(f, "R%02d=%08x", i, env->gr[i]);
+         if ((i % 4) == 3)
+             cpu_fprintf(f, "\n");
+         else
+             cpu_fprintf(f, " ");
+     }
+ 
+     for(i=0;i<31;i++) {
+         cpu_fprintf(f, "CR%02d=%08x", i, env->cr[i]);
+         if ((i % 4) == 3)
+             cpu_fprintf(f, "\n");
+         else
+             cpu_fprintf(f, " ");
+     }
+ 
+     cpu_fprintf(f, "IAOQ = %08X %08X\tIASQ = %08X %08X\n",
+                 env->iaoq[0], env->iaoq[1], env->iasq[0], env->iasq[1]);
+ }
+ 

Index: cpu.h
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/cpu.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** cpu.h	27 Feb 2007 23:21:24 -0000	1.2
--- cpu.h	4 Mar 2007 15:16:27 -0000	1.3
***************
*** 22,30 ****
  #define CPU_HPPA_H
  
  #define TARGET_LONG_BITS 32
  #include "cpu-defs.h"
  
  /* the shadow registers map to the following general registers */
! int shrmap[] = { 1, 6, 9, 16, 17, 24, 25 };
  
  #define PSW_Y   0x00000001
--- 22,38 ----
  #define CPU_HPPA_H
  
+ #include "config.h"
+ 
  #define TARGET_LONG_BITS 32
  #include "cpu-defs.h"
  
+ #include <setjmp.h>
+ 
+ #include "softfloat.h"
+ 
+ #define ELF_MACHINE	EM_PARISC
+ 
  /* the shadow registers map to the following general registers */
! // int shrmap[] = { 1, 6, 9, 16, 17, 24, 25 };
  
  #define PSW_Y   0x00000001
***************
*** 60,63 ****
--- 68,73 ----
  #define PSW_I   0x80000000
  
+ #define PSW_CB7_SHIFT	7	/* CHECK */
+ 
  typedef struct CPUHPPAState {
      target_ulong gr[32];  /* General Registers */
***************
*** 78,82 ****
--- 88,108 ----
    *  gr[31] : link register for BLE
    */
+ 
+     jmp_buf  jmp_env;
+     int user_mode_only;
+     int exception_index;
+     int interrupt_index;
+     int interrupt_request;
+     int halted;
+ 
+     CPU_COMMON
+ 
  } CPUHPPAState;
  
+ #define TARGET_PAGE_BITS 12
+ #include "cpu-all.h"
+ 
+ CPUHPPAState *cpu_hppa_init(void);
+ int cpu_hppa_exec(CPUHPPAState *s);
+ 
  #endif

Index: exec.h
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/exec.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** exec.h	2 Mar 2007 23:47:46 -0000	1.2
--- exec.h	4 Mar 2007 15:16:27 -0000	1.3
***************
*** 20,24 ****
--- 20,28 ----
   */
  
+ #ifndef EXEC_HPPA_H
+ #define EXEC_HPPA_H
+ 
  #include "dyngen-exec.h"
+ #include "config.h"
  
  register struct CPUHPPAState *env asm(AREG0);
***************
*** 28,29 ****
--- 32,44 ----
  
  #include "cpu.h"
+ #include "exec-all.h"
+ 
+ static inline void env_to_regs(void)
+ {
+ }
+ 
+ static inline void regs_to_env(void)
+ {
+ }
+ 
+ #endif

Index: op.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** op.c	2 Mar 2007 23:47:46 -0000	1.3
--- op.c	4 Mar 2007 15:16:27 -0000	1.4
***************
*** 21,24 ****
--- 21,27 ----
  #include "exec.h"
  
+ #define REGNAME gr0
+ #define REG (env->gr[0])
+ #include "op_template.h"
  #define REGNAME gr1
  #define REG (env->gr[1])
***************
*** 27,33 ****
  #define REG (env->gr[2])
  #include "op_template.h"
- #define REGNAME gr2
- #define REG (env->gr[2])
- #include "op_template.h"
  #define REGNAME gr3
  #define REG (env->gr[3])
--- 30,33 ----
***************
*** 118,145 ****
  #include "op_template.h"
  
! void OPPROTO op_mov_T0_GR0(void)
  {
  	T0 = 0;
  }
  
! void OPPROTO op_mov_T1_GR0(void)
  {
  	T1 = 0;
  }
  
! void OPPROTO op_mov_GR0_T0(void)
  {
  }
  
! void OPPROTO op_mov_GR0_T1(void)
  {
  }
  
! void OPPROTO op_mov_T0_im(void)
  {
  	T0 = PARAM1;
  }
  
! void OPPROTO op_mov_T1_im(void)
  {
  	T1 = PARAM1;
--- 118,145 ----
  #include "op_template.h"
  
! void OPPROTO op_movl_T0_GR0(void)
  {
  	T0 = 0;
  }
  
! void OPPROTO op_movl_T1_GR0(void)
  {
  	T1 = 0;
  }
  
! void OPPROTO op_movl_GR0_T0(void)
  {
  }
  
! void OPPROTO op_movl_GR0_T1(void)
  {
  }
  
! void OPPROTO op_movl_T0_im(void)
  {
  	T0 = PARAM1;
  }
  
! void OPPROTO op_movl_T1_im(void)
  {
  	T1 = PARAM1;
***************
*** 171,175 ****
      carry &= 0x000000ff;  /* 000000000000000000000000abcdefgh */
  
!     env->psw &= ~PSW_CB
      env->psw |= carry << PSW_CB7_SHIFT;
  }
--- 171,175 ----
      carry &= 0x000000ff;  /* 000000000000000000000000abcdefgh */
  
!     env->psw &= ~PSW_CB;
      env->psw |= carry << PSW_CB7_SHIFT;
  }
***************
*** 201,205 ****
      carry &= 0x000000ff;  /* 000000000000000000000000abcdefgh */
  
!     env->psw &= ~PSW_CB
      env->psw |= carry << PSW_CB7_SHIFT;
  }
--- 201,205 ----
      carry &= 0x000000ff;  /* 000000000000000000000000abcdefgh */
  
!     env->psw &= ~PSW_CB;
      env->psw |= carry << PSW_CB7_SHIFT;
  }
***************
*** 274,278 ****
      borrow &= 0x000000ff;   /* 000000000000000000000000abcdefgh */
  
!     env->psw &= ~PSW_CB
      env->psw |= ~borrow << PSW_CB7_SHIFT;
  }
--- 274,278 ----
      borrow &= 0x000000ff;   /* 000000000000000000000000abcdefgh */
  
!     env->psw &= ~PSW_CB;
      env->psw |= ~borrow << PSW_CB7_SHIFT;
  }
***************
*** 280,286 ****
  void OPPROTO op_next_insn(void)
  {
!     iaoq[0] = iaoq[1];
!     iasq[0] = iasq[1];
!     iaoq[1] += 4;
  }
  
--- 280,286 ----
  void OPPROTO op_next_insn(void)
  {
!     env->iaoq[0] = env->iaoq[1];
!     env->iasq[0] = env->iasq[1];
!     env->iaoq[1] += 4;
  }