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[HPPAQEMU-CVS] hppaqemu/target-hppa cpu.h, 1.1, 1.2 op.c, 1.1, 1.2 translate.c, 1.1, 1.2
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From: Stuart B. <zu...@us...> - 2007-02-27 23:21:27
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv14538 Modified Files: cpu.h op.c translate.c Log Message: Updated code from 2006-06-10. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** translate.c 27 Feb 2007 23:20:43 -0000 1.1 --- translate.c 27 Feb 2007 23:21:24 -0000 1.2 *************** *** 21,24 **** --- 21,34 ---- */ + #include "cpu.h" + #include "exec-all.h" + #include "disas.h" + + typedef struct DisasContext { + target_ulong iaoq[2]; + target_ulong iasq[2]; + struct TranslationBlock *tb; + } DisasContext; + static inline uint32_t field(uint32_t val, int start, int length) { val >>= start; *************** *** 246,250 **** int ext6; ! insn = ldl_code((uint8_t *)dc->pc); op = field(insn, 26, 6); --- 256,260 ---- int ext6; ! insn = ldl_code(dc->iaoq[0]); op = field(insn, 26, 6); *************** *** 642,646 **** case 0x24: /* COMICLR */ { ! uint32 r, t, c, f, im11; if (field(insn, 11, 1)) gen_op_undef_insn(); --- 652,656 ---- case 0x24: /* COMICLR */ { ! uint32_t r, t, c, f, im11; if (field(insn, 11, 1)) gen_op_undef_insn(); *************** *** 736,748 **** case 0x38: /* BE */ case 0x39: /* BLE */ break; case 0x3a: /* Branch */ { ! uint32_t ext3; ext3 = field(insn, 13, 3); switch(ext3) { case 0: /* BL */ case 2: /* BLR */ case 6: /* BV */ case 1: /* GATE */ --- 746,780 ---- case 0x38: /* BE */ case 0x39: /* BLE */ + { + uint32_t b, w1, s, w2, n, w; + b = field(insn, 21, 5); + w1 = field_signext(insn, 16, 5); + s = field(insn, 13, 3); + w2 = field(insn, 2, 11); + n = field(insn, 1, 1); + w = field(insn, 0, 1); + disp = (((((w1 << 11) | w2) << 1) | w) << 2); + /* */ break; + } case 0x3a: /* Branch */ { ! uint32_t t, w1, ext3, w2, n, disp; ext3 = field(insn, 13, 3); + t = field(insn, 21, 5); + w1 = field_signext(insn, 16, 5); + w2 = field(insn, 2, 11); + n = field(insn, 1, 1); + w = field(insn, 0, 1); + disp = (((((w1 << 11) | w2) << 1) | w) << 2); switch(ext3) { case 0: /* BL */ + /* generate (iaoq_next <- iaoq_front + disp + 8) */ + /* generate (copy iaoq_back + 4 into t) */ + /* if (n) generate (psw |= PSW_N); */ + break; case 2: /* BLR */ + /* if w == 0 ( ill_insn ) */ case 6: /* BV */ case 1: /* GATE */ Index: cpu.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/cpu.h,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** cpu.h 27 Feb 2007 23:20:43 -0000 1.1 --- cpu.h 27 Feb 2007 23:21:24 -0000 1.2 *************** *** 22,25 **** --- 22,28 ---- #define CPU_HPPA_H + #define TARGET_LONG_BITS 32 + #include "cpu-defs.h" + /* the shadow registers map to the following general registers */ int shrmap[] = { 1, 6, 9, 16, 17, 24, 25 }; *************** *** 58,71 **** typedef struct CPUHPPAState { ! uint32_t gr[32]; /* General Registers */ ! uint32_t shr[7]; /* SHadow Registers */ ! uint32_t sr[8]; /* Space Registers */ ! uint32_t cr[32]; /* Control Registers */ ! /* uint32_t cpr[n][8]; */ /* Co-Processor Registers */ ! uint32_t fpr[32]; /* Floating-Point Registers */ ! ! uint32_t psw; /* Processor Status Word */ ! uint32_t iaoq[2]; /* Instruction Address Offset Queue */ ! uint32_t iasq[2]; /* Instruction Address Space Queue */ /* gr[0] : permanently 0 --- 61,76 ---- typedef struct CPUHPPAState { ! target_ulong gr[32]; /* General Registers */ ! target_ulong shr[7]; /* SHadow Registers */ ! uint32_t sr[8]; /* Space Registers */ ! uint32_t cr[32]; /* Control Registers */ ! #if 0 ! uint32_t cpr[n][8]; /* Co-Processor Registers */ ! #endif ! uint32_t fpr[32]; /* Floating-Point Registers */ ! ! uint32_t psw; /* Processor Status Word */ ! target_ulong iaoq[2]; /* Instruction Address Offset Queue */ ! uint32_t iasq[2]; /* Instruction Address Space Queue */ /* gr[0] : permanently 0 Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** op.c 27 Feb 2007 23:20:43 -0000 1.1 --- op.c 27 Feb 2007 23:21:24 -0000 1.2 *************** *** 146,173 **** } ! void OPPROTO op_add_T1_T0(void) { ! uint32 src1; ! src1 = T0; T0 += T1; /* TODO: lazy PSW */ env->psw &= ~PSW_CB ! if((T0 & 0x0000000f) < (src1 & 0x0000000f)) ! env->psw |= PSW_CB0; ! if((T0 & 0x000000ff) < (src1 & 0x000000ff)) ! env->psw |= PSW_CB1; ! if((T0 & 0x00000fff) < (src1 & 0x00000fff)) ! env->psw |= PSW_CB2; ! if((T0 & 0x0000ffff) < (src1 & 0x0000ffff)) ! env->psw |= PSW_CB3; ! if((T0 & 0x000fffff) < (src1 & 0x000fffff)) ! env->psw |= PSW_CB4; ! if((T0 & 0x00ffffff) < (src1 & 0x00ffffff)) ! env->psw |= PSW_CB5; ! if((T0 & 0x0fffffff) < (src1 & 0x0fffffff)) ! env->psw |= PSW_CB6; ! if((T0 & 0xffffffff) < (src1 & 0xffffffff)) ! env->psw |= PSW_CB7; /* gen_op_add_T1_imm(1) -- for ADDC and ADDCO */ --- 146,204 ---- } ! /* TODO: lazy PSW */ ! void OPPROTO op_addc_T1_T0(void) { ! uint32_t mask; ! uint32_t pswbit; ! int carry; ! int i; ! T0 += T1; + /* add the carry */ + if (env->psw & PSW_CB7) { + T0 += 1; + carry = 1; + } else { + carry = 0; + } + + /* calculate carry flags */ + i = 0; + env->psw &= ~PSW_CB + mask = 0xffffffff; + pswbit = PSW_CB7; + while(i < 8) { + if(((T0 & mask) < (T1 & mask)) || + (carry && ((T0 & mask) == (T1 & mask)))) + env->psw |= pswbit; + pswbit >>= 1; + mask >>= 4; + mask &= 0x0fffffff; + i++; + } + } /* TODO: lazy PSW */ + void OPPROTO op_add_T1_T0(void) + { + uint32_t mask; + uint32_t pswbit; + int i; + + T0 += T1; + + /* calculate carry flags */ + i = 0; env->psw &= ~PSW_CB ! mask = 0xffffffff; ! pswbit = PSW_CB7; ! while(i < 8) { ! if((T0 & mask) < (T1 & mask)) ! env->psw |= pswbit; ! pswbit >>= 1; ! mask >>= 4; ! mask &= 0x0fffffff; ! i++; ! } /* gen_op_add_T1_imm(1) -- for ADDC and ADDCO */ |
