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[HPPAQEMU-CVS] hppaqemu/target-hppa cpu.h, NONE, 1.1 exec.h, NONE, 1.1 op.c, NONE, 1.1 op_mem.h, NONE, 1.1 op_template.h, NONE, 1.1 translate.c, NONE, 1.1
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From: Stuart B. <zu...@us...> - 2007-02-27 23:20:46
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv14299 Added Files: cpu.h exec.h op.c op_mem.h op_template.h translate.c Log Message: Initial HPPA target code from 2005. --- NEW FILE: translate.c --- /* * HPPA translation * * Copyright (c) 2005 Stuart Brady <sd...@nt...> * Copyright (c) 2003 Thomas M. Ogrisegg <to...@fn...> * Copyright (c) 2003 Fabrice Bellard * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ static inline uint32_t field(uint32_t val, int start, int length) { val >>= start; val &= ~(~0 << length); return val; } static inline uint32_t field_signext(uint32_t val, int start, int length) { val >>= start; if (val & (1 << (length - 1))) val |= ~0 << length; else val &= ~(~0 << length); return val; } static inline uint32_t signext(uint32_t val, int length) { if (val & (1 << (length - 1))) val |= ~0 << length; return val; } static GenOpFunc *gen_op_movl_TN_reg[2][32] = { { gen_op_movl_gr0_T0, gen_op_movl_gr1_T0, gen_op_movl_gr2_T0, gen_op_movl_gr3_T0, gen_op_movl_gr4_T0, gen_op_movl_gr5_T0, gen_op_movl_gr6_T0, gen_op_movl_gr7_T0, gen_op_movl_gr8_T0, gen_op_movl_gr9_T0, gen_op_movl_gr10_T0, gen_op_movl_gr11_T0, gen_op_movl_gr12_T0, gen_op_movl_gr13_T0, gen_op_movl_gr14_T0, gen_op_movl_gr15_T0, gen_op_movl_gr16_T0, gen_op_movl_gr17_T0, gen_op_movl_gr18_T0, gen_op_movl_gr19_T0, gen_op_movl_gr20_T0, gen_op_movl_gr21_T0, gen_op_movl_gr22_T0, gen_op_movl_gr23_T0, gen_op_movl_gr24_T0, gen_op_movl_gr25_T0, gen_op_movl_gr26_T0, gen_op_movl_gr27_T0, gen_op_movl_gr28_T0, gen_op_movl_gr29_T0, gen_op_movl_gr30_T0, gen_op_movl_gr31_T0, }, { gen_op_movl_gr0_T1, gen_op_movl_gr1_T1, gen_op_movl_gr2_T1, gen_op_movl_gr3_T1, gen_op_movl_gr4_T1, gen_op_movl_gr5_T1, gen_op_movl_gr6_T1, gen_op_movl_gr7_T1, gen_op_movl_gr8_T1, gen_op_movl_gr9_T1, gen_op_movl_gr10_T1, gen_op_movl_gr11_T1, gen_op_movl_gr12_T1, gen_op_movl_gr13_T1, gen_op_movl_gr14_T1, gen_op_movl_gr15_T1, gen_op_movl_gr16_T1, gen_op_movl_gr17_T1, gen_op_movl_gr18_T1, gen_op_movl_gr19_T1, gen_op_movl_gr20_T1, gen_op_movl_gr21_T1, gen_op_movl_gr22_T1, gen_op_movl_gr23_T1, gen_op_movl_gr24_T1, gen_op_movl_gr25_T1, gen_op_movl_gr26_T1, gen_op_movl_gr27_T1, gen_op_movl_gr28_T1, gen_op_movl_gr29_T1, gen_op_movl_gr30_T1, gen_op_movl_gr31_T1, } }; static GenOpFunc *gen_op_movl_reg_TN[2][32] = { { gen_op_movl_T0_gr0, gen_op_movl_T0_gr1, gen_op_movl_T0_gr2, gen_op_movl_T0_gr3, gen_op_movl_T0_gr4, gen_op_movl_T0_gr5, gen_op_movl_T0_gr6, gen_op_movl_T0_gr7, gen_op_movl_T0_gr8, gen_op_movl_T0_gr9, gen_op_movl_T0_gr10, gen_op_movl_T0_gr11, gen_op_movl_T0_gr12, gen_op_movl_T0_gr13, gen_op_movl_T0_gr14, gen_op_movl_T0_gr15, gen_op_movl_T0_gr16, gen_op_movl_T0_gr17, gen_op_movl_T0_gr18, gen_op_movl_T0_gr19, gen_op_movl_T0_gr20, gen_op_movl_T0_gr21, gen_op_movl_T0_gr22, gen_op_movl_T0_gr23, gen_op_movl_T0_gr24, gen_op_movl_T0_gr25, gen_op_movl_T0_gr26, gen_op_movl_T0_gr27, gen_op_movl_T0_gr28, gen_op_movl_T0_gr29, gen_op_movl_T0_gr30, gen_op_movl_T0_gr31, }, { gen_op_movl_T1_gr0, gen_op_movl_T1_gr1, gen_op_movl_T1_gr2, gen_op_movl_T1_gr3, gen_op_movl_T1_gr4, gen_op_movl_T1_gr5, gen_op_movl_T1_gr6, gen_op_movl_T1_gr7, gen_op_movl_T1_gr8, gen_op_movl_T1_gr9, gen_op_movl_T1_gr10, gen_op_movl_T1_gr11, gen_op_movl_T1_gr12, gen_op_movl_T1_gr13, gen_op_movl_T1_gr14, gen_op_movl_T1_gr15, gen_op_movl_T1_gr16, gen_op_movl_T1_gr17, gen_op_movl_T1_gr18, gen_op_movl_T1_gr19, gen_op_movl_T1_gr20, gen_op_movl_T1_gr21, gen_op_movl_T1_gr22, gen_op_movl_T1_gr23, gen_op_movl_T1_gr24, gen_op_movl_T1_gr25, gen_op_movl_T1_gr26, gen_op_movl_T1_gr27, gen_op_movl_T1_gr28, gen_op_movl_T1_gr29, gen_op_movl_T1_gr30, gen_op_movl_T1_gr31, } }; static GenOpFunc1 *gen_op_movl_TN_im[2] = { gen_op_movl_T0_im, gen_op_movl_T1_im, }; #define gen_op_ldst(name) gen_op_##name##_raw() static inline void gen_movl_imm_TN(int reg, int val) { gen_op_movl_TN_im[reg](val); } static inline void gen_movl_imm_T0(int val) { gen_movl_imm_T0(0, val); } static inline void gen_movl_imm_T1(int val) { gen_movl_imm_T1(1, val); } static inline void gen_movl_reg_TN(int reg, int t) { if (reg) gen_op_movl_reg_TN[t][reg] (); else gen_movl_imm_TN(t, 0); } static inline void gen_movl_reg_T0(int reg) { gen_movl_reg_TN(reg, 0); } static inline void gen_movl_reg_T1(int reg) { gen_movl_reg_TN(reg, 1); } static inline void gen_movl_TN_reg(int reg, int t) { if (reg) gen_op_movl_TN_reg[t][reg] (); } static inline void gen_movl_T0_reg(int reg) { gen_movl_TN_reg(reg, 0); } static inline void gen_movl_T1_reg(int reg) { gen_movl_TN_reg(reg, 1); } static void disas_hppa_insn(DisasContext * dc) { unsigned int insn; int op; int ext6; insn = ldl_code((uint8_t *)dc->pc); op = field(insn, 26, 6); /* TODO: * branches * nullification * conditions * carry * refactoring */ /* Major Opcodes */ switch(op) { case 0x00: /* System_op */ { uint32_t ext8; ext8 = field(insn, 5, 6); switch(ext8) { case 0x00: /* BREAK */ case 0x20: /* SYNC, SYNCDMAA */ case 0x60: /* RFI */ case 0x65: /* RFIR */ case 0x6b: /* SSM */ case 0x73: /* RSM */ case 0xc3: /* MTSM */ case 0x85: /* LDSID */ case 0xc1: /* MTSP */ case 0x25: /* MFSP */ case 0xc2: /* MTCTL */ case 0x45: /* MFCTL */ break; default: gen_op_undef_insn(); break; } break; } case 0x01: /* Mem_Mgmt */ { uint32_t ext5; ext5 = field(insn, 0, 5); if(!field(insn, 12, 1)) { uint32_t ext7; ext7 = field(insn, 6, 7); swtich(ext7) { case 0x01: /* IITLBA */ case 0x00: /* IITLBP */ case 0x08: /* PITLB */ case 0x09: /* PITLBE */ case 0x0a: /* FIC */ case 0x0b: /* FICE */ break; default: gen_op_undef_insn(); break; } } else { uint32_t ext7; ext8 = field(insn, 6, 8); { case 0x40: /* IDTLBP */ case 0x41: /* IDTLBA */ case 0x48: /* PDTLB */ case 0x49: /* PDTLBE */ case 0x4a: /* FDC */ case 0x4b: /* FDCE */ case 0x4e: /* PDC */ case 0x46: /* PROBER */ case 0xc6: /* PROBERI */ case 0x47: /* PROBEW */ case 0xc7: /* PROBEWI */ case 0x4d: /* LPA */ case 0x4c: /* LCI */ break; default: gen_op_undef_insn(); break; } } break; } case 0x02: /* Arith/Log */ { uint32_t t, r1, r2; r2 = field(insn, 21, 5); r1 = field(insn, 16, 5); ext6 = field(insn, 6, 6); t = field(insn, 0, 5); gen_movl_reg_T0(r1); gen_movl_reg_T1(r2); /* Opcode Extensions */ switch(ext6) { case 0x18: /* ADD */ gen_op_add_T1_T0(); break; case 0x38: /* ADDO */ gen_op_movl_T0_T2(); gen_op_addo_T1_T0(); /* if sign(T0) != sign(T1) && sign(T1) == sign(T2) overflow(); */ break; case 0x1C: /* ADDC */ gen_op_addc_T1_T0(); break; case 0x3C: /* ADDCO */ gen_op_addco_T1_T0(); break; case 0x19: /* SH1ADD */ gen_op_shift_T0(1); gen_op_add_T1_T0(); break; case 0x39: /* SH1ADDO */ gen_op_shift_T0(1); gen_op_addo_T1_T0(); break; case 0x1a: /* SH2ADD */ gen_op_shift_T0(2); gen_op_add_T1_T0(); break; case 0x3a: /* SH2ADDO */ gen_op_shift_T0(2); gen_op_addo_T1_T0(); break; case 0x1b: /* SH3ADD */ gen_op_shift_T0(3); gen_op_add_T1_T0(); break; case 0x3b: /* SH3ADDO */ gen_op_shift_T0(3); gen_op_addo_T1_T0(); break; case 0x10: /* SUB */ gen_op_sub_T1_T0(); break; case 0x30: /* SUBO */ gen_op_subo_T1_T0(); break; case 0x13: /* SUBT */ gen_op_subt_T1_T0(); break; case 0x33: /* SUBTO */ gen_op_subto_T1_T0(); break; case 0x14: /* SUBB */ gen_op_subb_T1_T0(); break; case 0x34: /* SUBBO */ gen_op_subbo_T1_T0(); break; case 0x11: /* DS */ gen_op_ds_T1_T0(); break; case 0x00: /* ANDCM */ gen_op_andcm_T1_T0(); break; case 0x08: /* AND */ gen_op_and_T1_T0(); break; case 0x09: /* OR */ gen_op_or_T1_T0(); break; case 0x0A: /* XOR */ gen_op_xor_T1_T0(); break; case 0x0E: /* UXOR */ gen_op_uxor_T1_T0(); break; case 0x22: /* COMCLR */ gen_op_comclr_T1_T0(); break; case 0x26: /* UADDCM */ genn_op_uaddcm_T1_T0(); break; case 0x27: /* UADDCMT */ genn_op_uaddcmt_T1_T0(); break; case 0x28: /* ADDL */ gen_op_addl_T1_T0(); break; case 0x29: /* SH1ADDL */ gen_op_shift_T0(1); gen_op_addl_T1_T0(); break; case 0x2A: /* SH2ADDL */ gen_op_shift_T0(2); gen_op_addl_T1_T0(); break; case 0x2B: /* SH3ADDL */ gen_op_shift_T0(3); gen_op_addl_T1_T0(); break; case 0x2E: /* DCOR */ if (r1 != 0) gen_op_undef_insn(); else gen_op_dcor_T0(); break; case 0x2F: /* IDCOR */ if (r1 != 0) gen_op_undef_insn(); else gen_op_idcor_T0(); break; default: /* Undefined Instruction */ gen_op_undef_insn(); break; } gen_movl_T0_reg(t); break; } case 0x03: /* Index_Mem */ { uint32_t ext4; ext4 = field(insn, 6, 4); if(field(insn, 12, 1)) { switch(ext4) { case 0x00: /* LDBX */ case 0x01: /* LDHX */ case 0x02: /* LDWX */ case 0x06: /* LDWAX */ case 0x07: /* LDCWX */ break; } } else { switch(ext4) { case 0x00: /* LDBS */ case 0x01: /* LDHS */ case 0x02: /* LDWS */ case 0x06: /* LDWAS */ case 0x07: /* LDCWS */ case 0x08: /* STBS */ case 0x09: /* STHS */ case 0x0a: /* STWS */ case 0x0c: /* STBYS */ case 0x0e: /* STWAS */ break; } } break; } case 0x04: /* SPOPn */ break; case 0x05: /* DIAG */ case 0x06: /* FMPYADD */ break; case 0x08: /* LDIL */ { uint32_t t, im21; t = field(insn, 21, 5); if(t) { im21 = field(insn, 0, 21) << (32 - 21); gen_movl_imm_T0(im21); gen_movl_reg_T0(t); } break; } case 0x09: /* Copr_w */ if(!field(insn, 12, 1)) if(!field(insn, 9, 1)) /* CLDWX */ {} else /* CSTWX */ {} else if(!field(insn, 9, 1)) /* CLDWS */ {} else /* CSTWS */ {} break; case 0x0a: /* ADDIL */ { uint32_t r, im21; r = field(insn, 21, 5); im21 = field(insn, 0, 21) << (32 - 21); gen_movl_T1_reg(r); gen_movl_imm_T0(im21); gen_op_add_T1_T0(); gen_movl_reg_T0(1); break; } case 0x0b: /* Copr_dw */ if(!field(insn, 12, 1)) if(!field(insn, 9, 1)) /* CLDDX */ {} else /* CSTDX */ {} else if(!field(insn, 9, 1)) /* CLDDS */ {} else /* CSTDS */ {} break; case 0x0c: /* COPR */ break; case 0x0d: /* LDO - Load Offset */ { uint32_t b, t, im14; b = field(insn, 21, 5); t = field(insn, 16, 5); im14 = field_signext(insn, 0, 14); gen_movl_reg_T0(b); gen_movl_imm_T1(im14); gen_add_T1_T0(); gen_movl_T0_reg(t); break; } case 0x0e: /* Float */ case 0x0f: /* Product Specific */ break; case 0x10: /* LDB */ case 0x11: /* LDH */ case 0x12: /* LDW */ { uint32_t b, t, s, im14; b = field(insn, 21, 5); t = field(insn, 16, 5); s = field(insn, 14, 2); im14 = field_signext(insn, 0, 14); gen_movl_reg_T0(b); gen_movl_imm_T1(s); /* gen_op_space_sel_T0_T1(); */ gen_movl_imm_T1(im14); gen_add_T1_T0(); switch(op) { case 0x10: /* LDB */ gen_op_ldst(ldb); break; case 0x11: /* LDH */ gen_op_ldst(ldh); break; case 0x12: /* LDW */ gen_op_ldst(ldw); break; } gen_movl_T1_reg(t); break; } case 0x13: /* LDWM */ break; case 0x18: /* STB */ case 0x19: /* STH */ case 0x1a: /* STW */ { uint32_t b, r, s, im14; b = field(insn, 21, 5); t = field(insn, 16, 5); s = field(insn, 14, 2); im14 = field_signext(insn, 0, 14); gen_movl_reg_T0(b); gen_movl_imm_T1(s); /* gen_op_space_sel_T0_T1(); */ gen_movl_imm_T1(im14); gen_add_T1_T0(); gen_movl_reg_T1(r); switch(op) { case 0x18: /* STB */ gen_op_ldst(stb); break; case 0x19: /* STH */ gen_op_ldst(sth); break; case 0x1a: /* STW */ gen_op_ldst(stw); break; } } case 0x1b: /* STWM */ case 0x20: /* COMBT */ case 0x21: /* COMIBT */ case 0x22: /* COMBF */ case 0x23: /* COMIBF */ break; case 0x24: /* COMICLR */ { uint32 r, t, c, f, im11; if (field(insn, 11, 1)) gen_op_undef_insn(); else { r = field(insn, 21, 5); t = field(insn, 16, 5); c = field(insn, 13, 3); f = field(insn, 12, 1); im11 = field_signext(insn, 0, 11); gen_movl_reg_T0(r); gen_movl_imm_T1(im11); gen_op_add_T1_T0(); gen_movl_imm_T0(0); gen_movl_TO_reg(t); break; } } case 0x25: /* SUBI, SUBIO */ { r = field(insn, 21, 5); t = field(insn, 16, 5); im11 = field_signext(insn, 0, 11); gen_movl_reg_T0(r); op_sub_T1_T0(); break; } case 0x26: /* FPYSUB */ case 0x28: /* ADDBT */ case 0x29: /* ADDIBT */ case 0x2a: /* ADDBF */ case 0x2b: /* ADDIBF */ break; case 0x2c: /* ADDIT, ADDIOT */ case 0x2d: /* ADDI, ADDIO */ { uint32_t r, t, im11; r = field(insn, 21, 5); t = field(insn, 16, 5); im11 = field_signext(insn, 0, 11); gen_movl_reg_T0(r); gen_movl_imm_T0(im11); if(!field(insn, 11, 1)) gen_op_addit_T0(); else gen_op_addito_T0(); gen_movl_T0_reg(t); break; } case 0x30: /* BVB */ case 0x31: /* BB */ case 0x32: /* MOVB */ case 0x33: /* MOVIB */ break; case 0x34: /* Extract */ { uint32_t ext3; ext3 = field(insn, 10, 3); switch(ext3) { case 0: /* VSHD */ case 2: /* SHD */ case 4: /* VEXTRU */ case 5: /* VEXTRS */ case 6: /* EXTRU */ case 7: /* EXTRS */ break; } break; } case 0x35: /* Deposit */ { uint32_t ext3; ext3 = field(insn, 10, 3); switch(ext3) { case 0: /* VZDEP */ case 1: /* VDEP */ case 2: /* ZDEP */ case 3: /* DEP */ case 4: /* VZDEPI */ case 5: /* VDEPI */ case 6: /* ZDEPI */ case 7: /* DEPI */ break; } break; } case 0x38: /* BE */ case 0x39: /* BLE */ break; case 0x3a: /* Branch */ { uint32_t ext3; ext3 = field(insn, 13, 3); switch(ext3) { case 0: /* BL */ case 2: /* BLR */ case 6: /* BV */ case 1: /* GATE */ break; } break; } default: /* Illegal Instruction */ gen_op_ill_insn(); break; } } --- NEW FILE: cpu.h --- /* * HPPA virtual CPU header * * Copyright (c) 2005 Stuart Brady <sd...@nt...> * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef CPU_HPPA_H #define CPU_HPPA_H /* the shadow registers map to the following general registers */ int shrmap[] = { 1, 6, 9, 16, 17, 24, 25 }; #define PSW_Y 0x00000001 #define PSW_Z 0x00000002 #define PSW_W 0x00000010 #define PSW_E 0x00000020 #define PSW_S 0x00000040 #define PSW_T 0x00000080 #define PSW_H 0x00000100 #define PSW_L 0x00000200 #define PSW_N 0x00000400 #define PSW_X 0x00000800 #define PSW_B 0x00001000 #define PSW_C 0x00002000 #define PSW_V 0x00004000 #define PSW_M 0x00008000 #define PSW_CB 0x00ff0000 #define PSW_CB0 0x00010000 #define PSW_CB1 0x00020000 #define PSW_CB2 0x00040000 #define PSW_CB3 0x00080000 #define PSW_CB4 0x00100000 #define PSW_CB5 0x00200000 #define PSW_CB6 0x00400000 #define PSW_CB7 0x00800000 #define PSW_O 0x01000000 #define PSW_G 0x02000000 #define PSW_F 0x04000000 #define PSW_R 0x08000000 #define PSW_Q 0x10000000 #define PSW_P 0x20000000 #define PSW_D 0x40000000 #define PSW_I 0x80000000 typedef struct CPUHPPAState { uint32_t gr[32]; /* General Registers */ uint32_t shr[7]; /* SHadow Registers */ uint32_t sr[8]; /* Space Registers */ uint32_t cr[32]; /* Control Registers */ /* uint32_t cpr[n][8]; */ /* Co-Processor Registers */ uint32_t fpr[32]; /* Floating-Point Registers */ uint32_t psw; /* Processor Status Word */ uint32_t iaoq[2]; /* Instruction Address Offset Queue */ uint32_t iasq[2]; /* Instruction Address Space Queue */ /* gr[0] : permanently 0 * gr[1] : target for ADDIL * gr[31] : link register for BLE */ } CPUHPPAState; #endif --- NEW FILE: op.c --- /* * HPPA micro operations * * Copyright (c) 2005 Stuart brady <sd...@nt...> * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include "exec.h" #define REGNAME gr1 #define REG (env->gr[1]) #include "op_template.h" #define REGNAME gr2 #define REG (env->gr[2]) #include "op_template.h" #define REGNAME gr2 #define REG (env->gr[2]) #include "op_template.h" #define REGNAME gr3 #define REG (env->gr[3]) #include "op_template.h" #define REGNAME gr4 #define REG (env->gr[4]) #include "op_template.h" #define REGNAME gr5 #define REG (env->gr[5]) #include "op_template.h" #define REGNAME gr6 #define REG (env->gr[6]) #include "op_template.h" #define REGNAME gr7 #define REG (env->gr[7]) #include "op_template.h" #define REGNAME gr8 #define REG (env->gr[8]) #include "op_template.h" #define REGNAME gr9 #define REG (env->gr[9]) #include "op_template.h" #define REGNAME gr10 #define REG (env->gr[10]) #include "op_template.h" #define REGNAME gr11 #define REG (env->gr[11]) #include "op_template.h" #define REGNAME gr12 #define REG (env->gr[12]) #include "op_template.h" #define REGNAME gr13 #define REG (env->gr[13]) #include "op_template.h" #define REGNAME gr14 #define REG (env->gr[14]) #include "op_template.h" #define REGNAME gr15 #define REG (env->gr[15]) #include "op_template.h" #define REGNAME gr16 #define REG (env->gr[16]) #include "op_template.h" #define REGNAME gr17 #define REG (env->gr[17]) #include "op_template.h" #define REGNAME gr18 #define REG (env->gr[18]) #include "op_template.h" #define REGNAME gr19 #define REG (env->gr[19]) #include "op_template.h" #define REGNAME gr20 #define REG (env->gr[20]) #include "op_template.h" #define REGNAME gr21 #define REG (env->gr[21]) #include "op_template.h" #define REGNAME gr22 #define REG (env->gr[22]) #include "op_template.h" #define REGNAME gr23 #define REG (env->gr[23]) #include "op_template.h" #define REGNAME gr24 #define REG (env->gr[24]) #include "op_template.h" #define REGNAME gr25 #define REG (env->gr[25]) #include "op_template.h" #define REGNAME gr26 #define REG (env->gr[26]) #include "op_template.h" #define REGNAME gr27 #define REG (env->gr[27]) #include "op_template.h" #define REGNAME gr28 #define REG (env->gr[28]) #include "op_template.h" #define REGNAME gr29 #define REG (env->gr[29]) #include "op_template.h" #define REGNAME gr30 #define REG (env->gr[30]) #include "op_template.h" #define REGNAME gr31 #define REG (env->gr[31]) #include "op_template.h" void OPPROTO op_mov_T0_GR0(void) { T0 = 0; } void OPPROTO op_mov_T1_GR0(void) { T1 = 0; } void OPPROTO op_mov_GR0_T0(void) { } void OPPROTO op_mov_GR0_T1(void) { } void OPPROTO op_mov_T0_im(void) { T0 = PARAM1; } void OPPROTO op_mov_T1_im(void) { T1 = PARAM1; } void OPPROTO op_add_T1_T0(void) { uint32 src1; src1 = T0; T0 += T1; /* TODO: lazy PSW */ env->psw &= ~PSW_CB if((T0 & 0x0000000f) < (src1 & 0x0000000f)) env->psw |= PSW_CB0; if((T0 & 0x000000ff) < (src1 & 0x000000ff)) env->psw |= PSW_CB1; if((T0 & 0x00000fff) < (src1 & 0x00000fff)) env->psw |= PSW_CB2; if((T0 & 0x0000ffff) < (src1 & 0x0000ffff)) env->psw |= PSW_CB3; if((T0 & 0x000fffff) < (src1 & 0x000fffff)) env->psw |= PSW_CB4; if((T0 & 0x00ffffff) < (src1 & 0x00ffffff)) env->psw |= PSW_CB5; if((T0 & 0x0fffffff) < (src1 & 0x0fffffff)) env->psw |= PSW_CB6; if((T0 & 0xffffffff) < (src1 & 0xffffffff)) env->psw |= PSW_CB7; /* gen_op_add_T1_imm(1) -- for ADDC and ADDCO */ /* overflow trap for ADDO */ /* set condition flags */ /* set nullify if condition met */ } void OPPROTO op_addl_T1_T0(void) { T0 += T1; /* if condition met, env->psw |= PSW_N */ } void OPPROTO op_add2_T1_T0(void) { T0 += T1; } void OPPROTO op_comclr_T1_T0(void) { /* T0 - T1; */ T0 = 0; } void OPPROTO op_or_T1_T0(void) { T0 |= T1; } void OPPROTO op_xor_T1_T0(void) { T0 ^= T1; } void OPPROTO op_and_T1_T0(void) { T0 &= T1; } void OPPROTO op_andcm_T1_T0(void) { T0 &= ~T1; } void OPPROTO op_next_insn(void) { iaoq[0] = iaoq[1]; iasq[0] = iasq[1]; iaoq[1] += 4; } #include "op_mem.h" --- NEW FILE: op_template.h --- /* * HPPA micro operations (templates for various register related * operations) * * Copyright (c) 2003 Fabrice Ballard * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ void OPPROTO glue(op_movl_T0_, REGNAME)(void) { T0 = REG; } void OPPROTO glue(op_movl_T1_, REGNAME)(void) { T1 = REG; } void OPPROTO glue(glue(op_movl_, REGNAME), _T0)(void) { REG = T0; } void OPPROTO glue(glue(op_movl_, REGNAME), _T1)(void) { REG = T1; } #undef REG #undef REGNAME --- NEW FILE: op_mem.h --- #define HPPA_LD_OP(name, qp) \ void OPPROTO glue(glue(op_, name), _raw)(void) \ { \ T1 = glue(qp, _raw)((void *)T0); \ } HPPA_LD_OP(ldw, ldl); HPPA_LD_OP(ldh, lduw); HPPA_LD_OP(ldb, ldub); #define HPPA_ST_OP(name, qp) \ void OPPROTO glue(glue(op_, name), _raw)(void) \ { \ glue(qp, _raw)((void *)T0, T1); \ } HPPA_ST_OP(stw, stl); HPPA_ST_OP(sth, stuw); HPPA_ST_OP(stb, stub); --- NEW FILE: exec.h --- /* * HPPA execution defines * * Copyright (c) 2005 Stuart Brady * Copyright (c) 2003 Fabrice Bellard * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include "dyngen-exec.h" register struct CPUHPPAState *env asm(AREG0); register uint32_t T0 asm(AREG1); register uint32_t T1 asm(AREG2); register uint32_t T2 asm(AREG3); #include "cpu.h" |
