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[HPPAQEMU-CVS] hppaqemu/fpu softfloat-native.c, 1.1.1.1, 1.2 softfloat-native.h, 1.1.1.1, 1.2 softfloat-specialize.h, 1.1.1.1, 1.2 softfloat.c, 1.1.1.1, 1.2 softfloat.h, 1.1.1.1, 1.2
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From: Stuart B. <zu...@us...> - 2008-02-18 00:14:27
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Update of /cvsroot/hppaqemu/hppaqemu/fpu In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv24609/fpu Modified Files: softfloat-native.c softfloat-native.h softfloat-specialize.h softfloat.c softfloat.h Log Message: Update to QEMU CVS from 2007-06-01. Index: softfloat-specialize.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/fpu/softfloat-specialize.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- softfloat-specialize.h 23 Feb 2007 21:44:14 -0000 1.1.1.1 +++ softfloat-specialize.h 18 Feb 2008 00:13:51 -0000 1.2 @@ -61,7 +61,11 @@ /*---------------------------------------------------------------------------- | The pattern for a default generated single-precision NaN. *----------------------------------------------------------------------------*/ +#if defined(TARGET_MIPS) || defined(TARGET_HPPA) +#define float32_default_nan 0xFF800000 +#else #define float32_default_nan 0xFFC00000 +#endif /*---------------------------------------------------------------------------- | Returns 1 if the single-precision floating-point value `a' is a NaN; @@ -70,9 +74,11 @@ int float32_is_nan( float32 a ) { - - return ( 0xFF000000 < (bits32) ( a<<1 ) ); - +#if defined(TARGET_MIPS) || defined(TARGET_HPPA) + return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF ); +#else + return ( 0xFF800000 <= (bits32) ( a<<1 ) ); +#endif } /*---------------------------------------------------------------------------- @@ -82,9 +88,11 @@ int float32_is_signaling_nan( float32 a ) { - +#if defined(TARGET_MIPS) || defined(TARGET_HPPA) + return ( 0xFF800000 <= (bits32) ( a<<1 ) ); +#else return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF ); - +#endif } /*---------------------------------------------------------------------------- @@ -131,8 +139,13 @@ aIsSignalingNaN = float32_is_signaling_nan( a ); bIsNaN = float32_is_nan( b ); bIsSignalingNaN = float32_is_signaling_nan( b ); +#if defined(TARGET_MIPS) || defined(TARGET_HPPA) + a &= ~0x00400000; + b &= ~0x00400000; +#else a |= 0x00400000; b |= 0x00400000; +#endif if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR); if ( aIsSignalingNaN ) { if ( bIsSignalingNaN ) goto returnLargerSignificand; @@ -154,7 +167,11 @@ /*---------------------------------------------------------------------------- | The pattern for a default generated double-precision NaN. *----------------------------------------------------------------------------*/ +#if defined(TARGET_MIPS) || defined(TARGET_HPPA) +#define float64_default_nan LIT64( 0xFFF0000000000000 ) +#else #define float64_default_nan LIT64( 0xFFF8000000000000 ) +#endif /*---------------------------------------------------------------------------- | Returns 1 if the double-precision floating-point value `a' is a NaN; @@ -163,9 +180,13 @@ int float64_is_nan( float64 a ) { - - return ( LIT64( 0xFFE0000000000000 ) < (bits64) ( a<<1 ) ); - +#if defined(TARGET_MIPS) || defined(TARGET_HPPA) + return + ( ( ( a>>51 ) & 0xFFF ) == 0xFFE ) + && ( a & LIT64( 0x0007FFFFFFFFFFFF ) ); +#else + return ( LIT64( 0xFFF0000000000000 ) <= (bits64) ( a<<1 ) ); +#endif } /*---------------------------------------------------------------------------- @@ -175,11 +196,13 @@ int float64_is_signaling_nan( float64 a ) { - +#if defined(TARGET_MIPS) || defined(TARGET_HPPA) + return ( LIT64( 0xFFF0000000000000 ) <= (bits64) ( a<<1 ) ); +#else return ( ( ( a>>51 ) & 0xFFF ) == 0xFFE ) && ( a & LIT64( 0x0007FFFFFFFFFFFF ) ); - +#endif } /*---------------------------------------------------------------------------- @@ -229,8 +252,13 @@ aIsSignalingNaN = float64_is_signaling_nan( a ); bIsNaN = float64_is_nan( b ); bIsSignalingNaN = float64_is_signaling_nan( b ); +#if defined(TARGET_MIPS) || defined(TARGET_HPPA) + a &= ~LIT64( 0x0008000000000000 ); + b &= ~LIT64( 0x0008000000000000 ); +#else a |= LIT64( 0x0008000000000000 ); b |= LIT64( 0x0008000000000000 ); +#endif if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR); if ( aIsSignalingNaN ) { if ( bIsSignalingNaN ) goto returnLargerSignificand; Index: softfloat.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/fpu/softfloat.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- softfloat.c 23 Feb 2007 21:44:15 -0000 1.1.1.1 +++ softfloat.c 18 Feb 2008 00:13:51 -0000 1.2 @@ -1164,6 +1164,27 @@ } +float32 uint64_to_float32( uint64 a STATUS_PARAM ) +{ + int8 shiftCount; + + if ( a == 0 ) return 0; + shiftCount = countLeadingZeros64( a ) - 40; + if ( 0 <= shiftCount ) { + return packFloat32( 1 > 0, 0x95 - shiftCount, a<<shiftCount ); + } + else { + shiftCount += 7; + if ( shiftCount < 0 ) { + shift64RightJamming( a, - shiftCount, &a ); + } + else { + a <<= shiftCount; + } + return roundAndPackFloat32( 1 > 0, 0x9C - shiftCount, a STATUS_VAR ); + } +} + /*---------------------------------------------------------------------------- | Returns the result of converting the 64-bit two's complement integer `a' | to the double-precision floating-point format. The conversion is performed @@ -1183,6 +1204,13 @@ } +float64 uint64_to_float64( uint64 a STATUS_PARAM ) +{ + if ( a == 0 ) return 0; + return normalizeRoundAndPackFloat64( 0, 0x43C, a STATUS_VAR ); + +} + #ifdef FLOATX80 /*---------------------------------------------------------------------------- @@ -5282,6 +5310,26 @@ return res; } +uint64_t float64_to_uint64 (float64 a STATUS_PARAM) +{ + int64_t v; + + v = int64_to_float64(INT64_MIN STATUS_VAR); + v = float64_to_int64((a + v) STATUS_VAR); + + return v - INT64_MIN; +} + +uint64_t float64_to_uint64_round_to_zero (float64 a STATUS_PARAM) +{ + int64_t v; + + v = int64_to_float64(INT64_MIN STATUS_VAR); + v = float64_to_int64_round_to_zero((a + v) STATUS_VAR); + + return v - INT64_MIN; +} + #define COMPARE(s, nan_exp) \ INLINE int float ## s ## _compare_internal( float ## s a, float ## s b, \ int is_quiet STATUS_PARAM ) \ Index: softfloat-native.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/fpu/softfloat-native.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- softfloat-native.c 23 Feb 2007 21:44:14 -0000 1.1.1.1 +++ softfloat-native.c 18 Feb 2008 00:13:51 -0000 1.2 @@ -30,6 +30,25 @@ #define sqrtf(f) ((float)sqrt(f)) #define remainderf(fa, fb) ((float)remainder(fa, fb)) #define rintf(f) ((float)rint(f)) +#if !defined(__sparc__) && defined(HOST_SOLARIS) && HOST_SOLARIS < 10 +extern long double rintl(long double); +extern long double scalbnl(long double, int); + +long long +llrintl(long double x) { + return ((long long) rintl(x)); +} + +long +lrintl(long double x) { + return ((long) rintl(x)); +} + +long double +ldexpl(long double x, int n) { + return (scalbnl(x, n)); +} +#endif #endif #if defined(__powerpc__) @@ -59,11 +78,21 @@ return (float32)v; } +float32 uint32_to_float32(unsigned int v STATUS_PARAM) +{ + return (float32)v; +} + float64 int32_to_float64(int v STATUS_PARAM) { return (float64)v; } +float64 uint32_to_float64(unsigned int v STATUS_PARAM) +{ + return (float64)v; +} + #ifdef FLOATX80 floatx80 int32_to_floatx80(int v STATUS_PARAM) { @@ -74,10 +103,18 @@ { return (float32)v; } +float32 uint64_to_float32( uint64_t v STATUS_PARAM) +{ + return (float32)v; +} float64 int64_to_float64( int64_t v STATUS_PARAM) { return (float64)v; } +float64 uint64_to_float64( uint64_t v STATUS_PARAM) +{ + return (float64)v; +} #ifdef FLOATX80 floatx80 int64_to_floatx80( int64_t v STATUS_PARAM) { @@ -132,6 +169,37 @@ } #endif +unsigned int float32_to_uint32( float32 a STATUS_PARAM) +{ + int64_t v; + unsigned int res; + + v = llrintf(a); + if (v < 0) { + res = 0; + } else if (v > 0xffffffff) { + res = 0xffffffff; + } else { + res = v; + } + return res; +} +unsigned int float32_to_uint32_round_to_zero( float32 a STATUS_PARAM) +{ + int64_t v; + unsigned int res; + + v = (int64_t)a; + if (v < 0) { + res = 0; + } else if (v > 0xffffffff) { + res = 0xffffffff; + } else { + res = v; + } + return res; +} + /*---------------------------------------------------------------------------- | Software IEC/IEEE single-precision operations. *----------------------------------------------------------------------------*/ @@ -218,9 +286,62 @@ } #endif +unsigned int float64_to_uint32( float64 a STATUS_PARAM) +{ + int64_t v; + unsigned int res; + + v = llrint(a); + if (v < 0) { + res = 0; + } else if (v > 0xffffffff) { + res = 0xffffffff; + } else { + res = v; + } + return res; +} +unsigned int float64_to_uint32_round_to_zero( float64 a STATUS_PARAM) +{ + int64_t v; + unsigned int res; + + v = (int64_t)a; + if (v < 0) { + res = 0; + } else if (v > 0xffffffff) { + res = 0xffffffff; + } else { + res = v; + } + return res; +} +uint64_t float64_to_uint64 (float64 a STATUS_PARAM) +{ + int64_t v; + + v = llrint(a + (float64)INT64_MIN); + + return v - INT64_MIN; +} +uint64_t float64_to_uint64_round_to_zero (float64 a STATUS_PARAM) +{ + int64_t v; + + v = (int64_t)(a + (float64)INT64_MIN); + + return v - INT64_MIN; +} + /*---------------------------------------------------------------------------- | Software IEC/IEEE double-precision operations. *----------------------------------------------------------------------------*/ +#if defined(__sun__) && defined(HOST_SOLARIS) && HOST_SOLARIS < 10 +static inline float64 trunc(float64 x) +{ + return x < 0 ? -floor(-x) : floor(x); +} +#endif float64 float64_trunc_to_int( float64 a STATUS_PARAM ) { return trunc(a); Index: softfloat-native.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/fpu/softfloat-native.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- softfloat-native.h 23 Feb 2007 21:44:14 -0000 1.1.1.1 +++ softfloat-native.h 18 Feb 2008 00:13:51 -0000 1.2 @@ -15,7 +15,7 @@ * Solaris 10 with GCC4 does not need these macros as they * are defined in <iso/math_c99.h> with a compiler directive */ -#if defined(HOST_SOLARIS) && (( HOST_SOLARIS <= 9 ) || ( ( HOST_SOLARIS >= 10 ) && ( __GNUC__ <= 4) )) +#if defined(HOST_SOLARIS) && (( HOST_SOLARIS <= 9 ) || ((HOST_SOLARIS >= 10) && (__GNUC__ <= 4))) /* * C99 7.12.3 classification macros * and @@ -33,6 +33,29 @@ #define isunordered(x,y) unordered(x, y) #endif +#if defined(__sun__) && !defined(NEED_LIBSUNMATH) + +#ifndef isnan +# define isnan(x) \ + (sizeof (x) == sizeof (long double) ? isnan_ld (x) \ + : sizeof (x) == sizeof (double) ? isnan_d (x) \ + : isnan_f (x)) +static inline int isnan_f (float x) { return x != x; } +static inline int isnan_d (double x) { return x != x; } +static inline int isnan_ld (long double x) { return x != x; } +#endif + +#ifndef isinf +# define isinf(x) \ + (sizeof (x) == sizeof (long double) ? isinf_ld (x) \ + : sizeof (x) == sizeof (double) ? isinf_d (x) \ + : isinf_f (x)) +static inline int isinf_f (float x) { return isnan (x - x); } +static inline int isinf_d (double x) { return isnan (x - x); } +static inline int isinf_ld (long double x) { return isnan (x - x); } +#endif +#endif + typedef float float32; typedef double float64; #ifdef FLOATX80 @@ -99,7 +122,9 @@ | Software IEC/IEEE integer-to-floating-point conversion routines. *----------------------------------------------------------------------------*/ float32 int32_to_float32( int STATUS_PARAM); +float32 uint32_to_float32( unsigned int STATUS_PARAM); float64 int32_to_float64( int STATUS_PARAM); +float64 uint32_to_float64( unsigned int STATUS_PARAM); #ifdef FLOATX80 floatx80 int32_to_floatx80( int STATUS_PARAM); #endif @@ -107,7 +132,9 @@ float128 int32_to_float128( int STATUS_PARAM); #endif float32 int64_to_float32( int64_t STATUS_PARAM); +float32 uint64_to_float32( uint64_t STATUS_PARAM); float64 int64_to_float64( int64_t STATUS_PARAM); +float64 uint64_to_float64( uint64_t v STATUS_PARAM); #ifdef FLOATX80 floatx80 int64_to_floatx80( int64_t STATUS_PARAM); #endif @@ -120,6 +147,8 @@ *----------------------------------------------------------------------------*/ int float32_to_int32( float32 STATUS_PARAM); int float32_to_int32_round_to_zero( float32 STATUS_PARAM); +unsigned int float32_to_uint32( float32 a STATUS_PARAM); +unsigned int float32_to_uint32_round_to_zero( float32 a STATUS_PARAM); int64_t float32_to_int64( float32 STATUS_PARAM); int64_t float32_to_int64_round_to_zero( float32 STATUS_PARAM); float64 float32_to_float64( float32 STATUS_PARAM); @@ -200,8 +229,12 @@ *----------------------------------------------------------------------------*/ int float64_to_int32( float64 STATUS_PARAM ); int float64_to_int32_round_to_zero( float64 STATUS_PARAM ); +unsigned int float64_to_uint32( float64 STATUS_PARAM ); +unsigned int float64_to_uint32_round_to_zero( float64 STATUS_PARAM ); int64_t float64_to_int64( float64 STATUS_PARAM ); int64_t float64_to_int64_round_to_zero( float64 STATUS_PARAM ); +uint64_t float64_to_uint64( float64 STATUS_PARAM ); +uint64_t float64_to_uint64_round_to_zero( float64 STATUS_PARAM ); float32 float64_to_float32( float64 STATUS_PARAM ); #ifdef FLOATX80 floatx80 float64_to_floatx80( float64 STATUS_PARAM ); Index: softfloat.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/fpu/softfloat.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- softfloat.h 23 Feb 2007 21:44:15 -0000 1.1.1.1 +++ softfloat.h 18 Feb 2008 00:13:51 -0000 1.2 @@ -32,6 +32,10 @@ #ifndef SOFTFLOAT_H #define SOFTFLOAT_H +#if defined(HOST_SOLARIS) && defined(NEEDS_LIBSUNMATH) +#include <sunmath.h> +#endif + #include <inttypes.h> #include "config.h" @@ -193,7 +197,9 @@ float128 int32_to_float128( int STATUS_PARAM ); #endif float32 int64_to_float32( int64_t STATUS_PARAM ); +float32 uint64_to_float32( uint64_t STATUS_PARAM ); float64 int64_to_float64( int64_t STATUS_PARAM ); +float64 uint64_to_float64( uint64_t STATUS_PARAM ); #ifdef FLOATX80 floatx80 int64_to_floatx80( int64_t STATUS_PARAM ); #endif @@ -236,8 +242,8 @@ int float32_lt_quiet( float32, float32 STATUS_PARAM ); int float32_compare( float32, float32 STATUS_PARAM ); int float32_compare_quiet( float32, float32 STATUS_PARAM ); +int float32_is_nan( float32 ); int float32_is_signaling_nan( float32 ); -int float64_is_nan( float64 a ); INLINE float32 float32_abs(float32 a) { @@ -258,6 +264,8 @@ unsigned int float64_to_uint32_round_to_zero( float64 STATUS_PARAM ); int64_t float64_to_int64( float64 STATUS_PARAM ); int64_t float64_to_int64_round_to_zero( float64 STATUS_PARAM ); +uint64_t float64_to_uint64 (float64 a STATUS_PARAM); +uint64_t float64_to_uint64_round_to_zero (float64 a STATUS_PARAM); float32 float64_to_float32( float64 STATUS_PARAM ); #ifdef FLOATX80 floatx80 float64_to_floatx80( float64 STATUS_PARAM ); @@ -285,6 +293,7 @@ int float64_lt_quiet( float64, float64 STATUS_PARAM ); int float64_compare( float64, float64 STATUS_PARAM ); int float64_compare_quiet( float64, float64 STATUS_PARAM ); +int float64_is_nan( float64 a ); int float64_is_signaling_nan( float64 ); INLINE float64 float64_abs(float64 a) @@ -328,6 +337,7 @@ int floatx80_eq_signaling( floatx80, floatx80 STATUS_PARAM ); int floatx80_le_quiet( floatx80, floatx80 STATUS_PARAM ); int floatx80_lt_quiet( floatx80, floatx80 STATUS_PARAM ); +int floatx80_is_nan( floatx80 ); int floatx80_is_signaling_nan( floatx80 ); INLINE floatx80 floatx80_abs(floatx80 a) @@ -375,6 +385,7 @@ int float128_eq_signaling( float128, float128 STATUS_PARAM ); int float128_le_quiet( float128, float128 STATUS_PARAM ); int float128_lt_quiet( float128, float128 STATUS_PARAM ); +int float128_is_nan( float128 ); int float128_is_signaling_nan( float128 ); INLINE float128 float128_abs(float128 a) |
