[HPPAQEMU-CVS] hppaqemu/target-sh4 helper.c, 1.1.1.1, 1.2 op.c, 1.1.1.1, 1.2 translate.c, 1.1.1.1, 1.2

[Stuart B. <zu...@us...>]

Update of /cvsroot/hppaqemu/hppaqemu/target-sh4
In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv24609/target-sh4

Modified Files:
	helper.c op.c translate.c 
Log Message:
Update to QEMU CVS from 2007-06-01.


Index: translate.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-sh4/translate.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- translate.c	23 Feb 2007 21:44:41 -0000	1.1.1.1
+++ translate.c	18 Feb 2008 00:14:00 -0000	1.2
@@ -236,7 +236,7 @@
 		? (x) + 16 : (x))
 
 #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
-#define XHACK(x) (((x) & 1 ) << 4 | ((x) & 0xe ) << 1)
+#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
 #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
 
 #define CHECK_NOT_DELAY_SLOT \
@@ -685,7 +685,7 @@
 	} else {
 	    gen_op_movl_rN_T0(REG(B7_4));
 	    gen_op_ldfl_T0_FT0(ctx);
-	    gen_op_fmov_FT0_frN(XREG(B11_8));
+	    gen_op_fmov_FT0_frN(FREG(B11_8));
 	}
 	return;
     case 0xf009:		/* fmov @Rm+,{F,D,X}Rn */
@@ -704,7 +704,7 @@
 	} else {
 	    gen_op_movl_rN_T0(REG(B7_4));
 	    gen_op_ldfl_T0_FT0(ctx);
-	    gen_op_fmov_FT0_frN(XREG(B11_8));
+	    gen_op_fmov_FT0_frN(FREG(B11_8));
 	    gen_op_inc4_rN(REG(B7_4));
 	}
 	return;
@@ -745,7 +745,7 @@
 	    gen_op_movl_rN_T0(REG(B7_4));
 	    gen_op_add_rN_T0(REG(0));
 	    gen_op_ldfl_T0_FT0(ctx);
-	    gen_op_fmov_FT0_frN(XREG(B11_8));
+	    gen_op_fmov_FT0_frN(FREG(B11_8));
 	}
 	return;
     case 0xf007:		/* fmov {F,D,X}Rn,@(R0,Rn) */
@@ -1003,8 +1003,8 @@
 	LDST(mach, 0x400a, 0x4006, lds, 0x000a, 0x4002, sts,)
 	LDST(macl, 0x401a, 0x4016, lds, 0x001a, 0x4012, sts,)
 	LDST(pr, 0x402a, 0x4026, lds, 0x002a, 0x4022, sts,)
-	LDST(fpul, 0x405a, 0x4056, lds, 0x005a, 0x0052, sts,)
-	LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x0062, sts, ctx->flags |=
+	LDST(fpul, 0x405a, 0x4056, lds, 0x005a, 0x4052, sts,)
+	LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x4062, sts, ctx->flags |=
 	     MODE_CHANGE;)
     case 0x00c3:		/* movca.l R0,@Rm */
 	gen_op_movl_rN_T0(REG(0));
@@ -1087,8 +1087,9 @@
     ctx->flags |= BRANCH_EXCEPTION;
 }
 
-int gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
-				   int search_pc)
+static inline int
+gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
+                               int search_pc)
 {
     DisasContext ctx;
     target_ulong pc_start;

Index: helper.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-sh4/helper.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- helper.c	23 Feb 2007 21:44:41 -0000	1.1.1.1
+++ helper.c	18 Feb 2008 00:14:00 -0000	1.2
@@ -53,7 +53,7 @@
     return 1;
 }
 
-target_ulong cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
 {
     return addr;
 }
@@ -429,7 +429,7 @@
     return tlb_set_page(env, address, physical, prot, is_user, is_softmmu);
 }
 
-target_ulong cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
 {
     target_ulong physical;
     int prot;

Index: op.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-sh4/op.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- op.c	23 Feb 2007 21:44:41 -0000	1.1.1.1
+++ op.c	18 Feb 2008 00:14:00 -0000	1.2
@@ -561,14 +561,14 @@
 void OPPROTO op_shar_Rn(void)
 {
     cond_t(env->gregs[PARAM1] & 1);
-    *(int32_t *) & env->gregs[PARAM1] >>= 1;
+    env->gregs[PARAM1] >>= 1;
     RETURN();
 }
 
 void OPPROTO op_shlr_Rn(void)
 {
     cond_t(env->gregs[PARAM1] & 1);
-    *(uint32_t *) & env->gregs[PARAM1] >>= 1;
+    env->gregs[PARAM1] >>= 1;
     RETURN();
 }
 
@@ -592,19 +592,19 @@
 
 void OPPROTO op_shlr2_Rn(void)
 {
-    *(uint32_t *) & env->gregs[PARAM1] >>= 2;
+    env->gregs[PARAM1] >>= 2;
     RETURN();
 }
 
 void OPPROTO op_shlr8_Rn(void)
 {
-    *(uint32_t *) & env->gregs[PARAM1] >>= 8;
+    env->gregs[PARAM1] >>= 8;
     RETURN();
 }
 
 void OPPROTO op_shlr16_Rn(void)
 {
-    *(uint32_t *) & env->gregs[PARAM1] >>= 16;
+    env->gregs[PARAM1] >>= 16;
     RETURN();
 }
 
@@ -737,7 +737,7 @@
 
 void OPPROTO op_dec8_rN(void)
 {
-    env->gregs[PARAM1] -= 4;
+    env->gregs[PARAM1] -= 8;
     RETURN();
 }
 
@@ -761,7 +761,7 @@
 
 void OPPROTO op_inc8_rN(void)
 {
-    env->gregs[PARAM1] += 4;
+    env->gregs[PARAM1] += 8;
     RETURN();
 }