Menu
▾
▴
hppaqemu-cvs
|
From: Stuart B. <zu...@us...> - 2008-02-23 14:29:27
|
Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv21684 Modified Files: translate.c Log Message: Coding style fixes. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.49 retrieving revision 1.50 diff -u -d -r1.49 -r1.50 --- translate.c 23 Feb 2008 01:33:59 -0000 1.49 +++ translate.c 23 Feb 2008 14:29:23 -0000 1.50 @@ -64,13 +64,15 @@ static void disas_hppa_insn(DisasContext * dc); -static uint32_t field(uint32_t val, int start, int length) { +static uint32_t field(uint32_t val, int start, int length) +{ val >>= start; val &= ~(~0 << length); return val; } -static int32_t field_signext(uint32_t val, int start, int length) { +static int32_t field_signext(uint32_t val, int start, int length) +{ val >>= start; if (val & (1 << (length - 1))) val |= ~0 << length; @@ -79,7 +81,8 @@ return val; } -static int32_t field_lowsignext(uint32_t val, int start, int length) { +static int32_t field_lowsignext(uint32_t val, int start, int length) +{ if (val & (1 << start)) { val >>= start + 1; val |= ~0 << (length - 1); @@ -90,21 +93,25 @@ return val; } -static int32_t signext(uint32_t val, int length) { +static int32_t signext(uint32_t val, int length) +{ if (val & (1 << (length - 1))) val |= ~0 << length; return val; } -static uint32_t assemble_12(uint32_t x, uint32_t y) { +static uint32_t assemble_12(uint32_t x, uint32_t y) +{ return (y << 11) | ((x & 1) << 10) | ((x >> 1) & ~(~0 << 10)); } -static uint32_t assemble_17(uint32_t x, uint32_t y, uint32_t z) { +static uint32_t assemble_17(uint32_t x, uint32_t y, uint32_t z) +{ return (z << 16) | (x << 11) | ((y & 1) << 10) | ((y >> 1) & ~(~0 << 10)); } -static uint32_t assemble_21(uint32_t x) { +static uint32_t assemble_21(uint32_t x) +{ return ((x & 1) << 20) | (((x >> 1) & ~(~0 << 11)) << 9) | (((x >> 14) & ~(~0 << 2)) << 7) | @@ -539,7 +546,7 @@ /* General registers */ static void gen_movl_reg_TN(int reg, int t) { - gen_op_movl_reg_TN[t][reg] (); + gen_op_movl_reg_TN[t][reg](); } static void gen_movl_reg_T0(int reg) @@ -559,7 +566,7 @@ static void gen_movl_TN_reg(int reg, int t) { - gen_op_movl_TN_reg[t][reg] (); + gen_op_movl_TN_reg[t][reg](); } static void gen_movl_T0_reg(int reg) @@ -661,6 +668,7 @@ } } +static void gen_branch(DisasContext *dc, long tb, static void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc) { gen_goto_tb(dc, tb, pc, npc); @@ -750,7 +758,8 @@ gen_op_eval_log_ev, }; -static void gen_branch_cond(DisasContext *dc, long tb, target_ulong disp, int n, int f) +static void gen_branch_cond(DisasContext *dc, long tb, target_ulong disp, + int n, int f) { int l1; target_ulong target; @@ -807,8 +816,8 @@ } static int gen_intermediate_code_internal(CPUState *env, - TranslationBlock *tb, - int search_pc) + TranslationBlock *tb, + int search_pc) { target_ulong pc_start, last_pc; uint16_t *gen_opc_end; @@ -827,10 +836,9 @@ gen_opparam_ptr = gen_opparam_buf; nb_gen_labels = 0; - while (!dc->is_br && gen_opc_ptr < gen_opc_end) - { + while (!dc->is_br && gen_opc_ptr < gen_opc_end) { if (env->nb_breakpoints > 0) { - for(j = 0; j < env->nb_breakpoints; j++) { + for (j = 0; j < env->nb_breakpoints; j++) { if (env->breakpoints[j] == dc->iaoq[0]) { save_state(dc); gen_op_debug(); @@ -865,14 +873,11 @@ if (env->singlestep_enabled) break; } - if (env->singlestep_enabled) - { + if (env->singlestep_enabled) { save_state(dc); gen_op_debug(); goto exit_gen_loop; - } - else if (!dc->is_br) - { + } else if (!dc->is_br) { save_state(dc); gen_goto_tb(dc, 0, dc->iaoq[0], dc->iaoq[1]); gen_op_exit_tb(); @@ -934,8 +939,7 @@ static int get_ldst_cmplt(uint32_t insn) { int indexed_load = (field(insn, 12, 1) == 0); - if (indexed_load) - { + if (indexed_load) { int u = field(insn, 13, 1); int m = field(insn, 5, 1); @@ -947,9 +951,7 @@ return LDST_CMPLT_S; else if (u == 1 && m == 1) return LDST_CMPLT_SM; - } - else - { + } else { int a = field(insn, 13, 1); int m = field(insn, 5, 1); uint32_t ext4 = field(insn, 6, 4); @@ -978,11 +980,9 @@ /* load value at address T0 to T1 */ - if (indexed_load) - { + if (indexed_load) { int x = field(insn, 16, 5); - switch (cmplt) - { + switch (cmplt) { case LDST_CMPLT_S: case LDST_CMPLT_SM: gen_movl_T0_reg(x); @@ -993,15 +993,12 @@ gen_movl_T0_reg(x); break; } - } - else - { + } else { target_long im5 = field_lowsignext(insn, 16, 5); gen_movl_T0_im(im5); } - switch (cmplt) - { + switch (cmplt) { case LDST_CMPLT_MB: /* dx in T0 */ gen_movl_T1_reg(b); @@ -1041,8 +1038,7 @@ /* store T1 at address T0 */ gen_movl_T0_im(im5); - switch (cmplt) - { + switch (cmplt) { case LDST_CMPLT_MB: gen_movl_T1_reg(b); gen_op_copy_T2_T0(); /* T2 = dx */ @@ -1143,12 +1139,12 @@ */ /* Major Opcodes */ - switch(op) { + switch (op) { case 0x00: /* System_op */ { int ext8; ext8 = field(insn, 5, 6); - switch(ext8) { + switch (ext8) { case 0x00: /* BREAK */ gen_op_break(); break; @@ -1232,8 +1228,7 @@ break; if (t != 11) gen_op_check_priv0(); - switch (t) - { + switch (t) { case 0: /* recovery counter */ /* TODO: mask 32-bits for 64-bit op */ case 14: @@ -1296,19 +1291,14 @@ if (r == 16) /* interval timer */ gen_op_check_int_timer_priv(); - if ((r >= 17 && r <= 22) || (r == 0)) - { + if ((r >= 17 && r <= 22) || (r == 0)) { gen_movl_T0_cr(r); gen_movl_reg_T0(t); - } - else if (r == 11) /* SAR */ - { + } else if (r == 11) { /* SAR */ /* Check - may need to mask and shift */ gen_movl_T0_cr(r); gen_movl_reg_T0(t); - } - else if (r >= 8) - { + } else if (r >= 8) { gen_movl_T0_cr(r); gen_movl_reg_T0(t); } @@ -1326,11 +1316,10 @@ { int ext5; ext5 = field(insn, 0, 5); - if(!field(insn, 12, 1)) { + if (!field(insn, 12, 1)) { int ext7; ext7 = field(insn, 6, 7); - switch(ext7) - { + switch (ext7) { case 0x08: /* PITLB */ case 0x09: /* PITLBE */ case 0x0a: /* FIC,0A (FIC) */ @@ -1352,8 +1341,7 @@ int ext8; ext8 = field(insn, 6, 8); - switch (ext8) - { + switch (ext8) { case 0x48: /* PDTLB */ case 0x49: /* PDTLBE */ case 0x4a: /* FDC (index) */ @@ -1396,7 +1384,7 @@ gen_movl_T1_reg(r2); /* Opcode Extensions */ - switch(ext6) { + switch (ext6) { case 0x18: /* ADD */ if (c || f) gen_cond_add[c](); @@ -1619,7 +1607,7 @@ case 0x03: /* Index_Mem */ { int ext4 = field(insn, 6, 4); - switch(ext4) { + switch (ext4) { /* XXX: gen_op_*_raw only works for user-mode emulation * we really need gen_load and gen_store to be macros * to allow _phys and _virtual to be used @@ -1686,7 +1674,7 @@ int t; target_ulong im21; t = field(insn, 21, 5); - if(t) { + if (t) { im21 = assemble_21(field(insn, 0, 21)) << (32 - 21); gen_movl_T0_im(im21); gen_movl_reg_T0(t); @@ -1695,13 +1683,13 @@ } case 0x09: /* Copr_w */ - if(!field(insn, 12, 1)) - if(!field(insn, 9, 1)) + if (!field(insn, 12, 1)) + if (!field(insn, 9, 1)) /* CLDW (index) (CLDWX) */ {} else /* CSTW (index) (CSTWX) */ {} else - if(!field(insn, 9, 1)) + if (!field(insn, 9, 1)) /* CLDW (short) (CLDWS) */ {} else /* CSTW (short) (CSTWS) */ {} @@ -1721,13 +1709,13 @@ } case 0x0b: /* Copr_dw */ - if(!field(insn, 12, 1)) - if(!field(insn, 9, 1)) + if (!field(insn, 12, 1)) + if (!field(insn, 9, 1)) /* CLDD (index) (CLDDX) */ {} else /* CSTD (index) (CLTDX) */ {} else - if(!field(insn, 9, 1)) + if (!field(insn, 9, 1)) /* CLDD (short) (CLDDS) */ {} else /* CSTD (short) (CSTDS) */ {} @@ -1769,7 +1757,7 @@ /* gen_op_space_sel_T0_T1(); */ gen_movl_T1_im(im14); gen_op_addl_T1_T0(); - switch(op) { + switch (op) { case 0x10: /* LDB */ gen_op_ldst(ldb); break; @@ -1796,13 +1784,13 @@ /* gen_movl_T1_im(s); */ /* gen_op_space_sel_T0_T1(); */ /* XXX: check this */ - if(im14 & (1 << 31)) { + if (im14 & (1 << 31)) { gen_movl_T1_im(im14); gen_op_addl_T1_T0(); } gen_op_ldst(ldw); gen_movl_reg_T1(t); - if(!(im14 & (1 << 31))) { + if (!(im14 & (1 << 31))) { gen_movl_T1_im(im14); gen_op_addl_T1_T0(); } @@ -1836,7 +1824,7 @@ gen_movl_T1_im(im14); gen_op_addl_T1_T0(); gen_movl_T1_reg(r); - switch(op) { + switch (op) { case 0x18: /* STB */ gen_op_ldst(stb); break; @@ -1862,13 +1850,13 @@ /* gen_movl_T1_im(s); */ /* gen_op_space_sel_T0_T1(); */ /* XXX: check this */ - if(im14 & (1 << 31)) { + if (im14 & (1 << 31)) { gen_movl_T1_im(im14); gen_op_addl_T1_T0(); } gen_movl_T1_reg(r); gen_op_ldst(stw); - if(!(im14 & (1 << 31))) { + if (!(im14 & (1 << 31))) { gen_movl_T1_im(im14); gen_op_addl_T1_T0(); } @@ -1893,7 +1881,7 @@ { int f, c, w1, n, w; target_long disp; - switch(op) { + switch (op) { case 0x20: /* CMPB (true) (COMBT) */ case 0x22: /* CMPB (false) (COMBF) */ { @@ -1994,7 +1982,7 @@ { int f, c, w1, n, w; target_long disp; - switch(op) { + switch (op) { case 0x28: /* ADDB (true) (ADDBT) */ case 0x2a: /* ADDB (false) (ADDBF) */ { @@ -2080,7 +2068,7 @@ { int ext3; ext3 = field(insn, 10, 3); - switch(ext3) { + switch (ext3) { case 0: /* VSHD = SHRPW with SAR */ gen_movl_T0_cr(11); gen_shrpw(insn); @@ -2113,7 +2101,7 @@ { int ext3; ext3 = field(insn, 10, 3); - switch(ext3) { + switch (ext3) { case 0: /* VZDEP = DEPW,Z with SAR */ case 1: /* VDEP = DEPW with SAR */ gen_movl_T0_cr(11); @@ -2179,7 +2167,7 @@ n = field(insn, 1, 1); w = field(insn, 0, 1); disp = signext(assemble_17(w1,w2,w),17) << 2; - switch(ext3) { + switch (ext3) { case 0: /* B,L (BL) */ /* TODO: dc->iaoq[1] + 4 into t */ if (n) { @@ -2248,7 +2236,7 @@ int i; cpu_fprintf(f, "PSW = %08X\n", env->psw); - for(i=0;i<31;i++) { + for (i=0; i<31; i++) { cpu_fprintf(f, "R%02d=%08x", i, env->gr[i]); if ((i % 4) == 3) cpu_fprintf(f, "\n"); @@ -2256,7 +2244,7 @@ cpu_fprintf(f, " "); } - for(i=0;i<31;i++) { + for (i=0; i<31; i++) { cpu_fprintf(f, "CR%02d=%08x", i, env->cr[i]); if ((i % 4) == 3) cpu_fprintf(f, "\n"); |
×
Want the latest updates on software, tech news, and AI?
Get latest updates about software, tech news, and AI from SourceForge directly in your inbox once a month.
Thanks for helping keep SourceForge clean.
X