hppaqemu-cvs

[Stuart B. <zu...@us...>]

Update of /cvsroot/hppaqemu/hppaqemu/target-hppa
In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv4348/target-hppa

Modified Files:
	op.c translate.c 
Log Message:
Make the ordering of operands in microop names more consistent.

Fix BL (branch and link).


Index: translate.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v
retrieving revision 1.17
retrieving revision 1.18
diff -C2 -d -r1.17 -r1.18
*** translate.c	12 Mar 2007 14:41:14 -0000	1.17
--- translate.c	12 Mar 2007 15:50:26 -0000	1.18
***************
*** 844,849 ****
              gen_movl_T1_reg(b);
              gen_op_copy_T2_T0();  /* copy dx to T2 */
!             gen_op_addl_T0_T1();  /* T0 = GR[b] + dx */
!             gen_op_addl_T1_T2();  /* GR[b] += dx */
              gen_movl_reg_T1(b);
              break;
--- 844,849 ----
              gen_movl_T1_reg(b);
              gen_op_copy_T2_T0();  /* copy dx to T2 */
!             gen_op_addl_T1_T0();  /* T0 = GR[b] + dx */
!             gen_op_addl_T2_T1();  /* GR[b] += dx */
              gen_movl_reg_T1(b);
              break;
***************
*** 854,858 ****
              gen_movl_T1_reg(b);
              gen_op_copy_T2_T1();
!             gen_op_addl_T1_T0();  /* GR[b] += dx */
              gen_movl_reg_T1(b);
              gen_op_copy_T0_T2();  /* T0 = GR[b] */
--- 854,858 ----
              gen_movl_T1_reg(b);
              gen_op_copy_T2_T1();
!             gen_op_addl_T0_T1();  /* GR[b] += dx */
              gen_movl_reg_T1(b);
              gen_op_copy_T0_T2();  /* T0 = GR[b] */
***************
*** 861,865 ****
              /* dx in T0 */
              gen_movl_T1_reg(b);
!             gen_op_addl_T0_T1();  /* T0 = GR[b] + dx */
              break;
      }
--- 861,865 ----
              /* dx in T0 */
              gen_movl_T1_reg(b);
!             gen_op_addl_T1_T0();  /* T0 = GR[b] + dx */
              break;
      }
***************
*** 884,889 ****
  	    gen_movl_T1_reg(b);
  	    gen_op_copy_T2_T0(); /* T2 = dx */
! 	    gen_op_addl_T0_T1(); /* offset = GR[b] + dx */
! 	    gen_op_addl_T1_T2(); /* GR[b] += dx */
  	    gen_movl_reg_T1(b);
  	    break;
--- 884,889 ----
  	    gen_movl_T1_reg(b);
  	    gen_op_copy_T2_T0(); /* T2 = dx */
! 	    gen_op_addl_T1_T0(); /* offset = GR[b] + dx */
! 	    gen_op_addl_T2_T1(); /* GR[b] += dx */
  	    gen_movl_reg_T1(b);
  	    break;
***************
*** 891,895 ****
  	    gen_movl_T1_reg(b);
  	    gen_op_copy_T2_T1(); /* T2 = GR[b] */
! 	    gen_op_addl_T1_T0(); /* GR[b] += dx */
  	    gen_movl_reg_T1(b);
  	    gen_op_copy_T0_T2(); /* offset = GR[b] */
--- 891,895 ----
  	    gen_movl_T1_reg(b);
  	    gen_op_copy_T2_T1(); /* T2 = GR[b] */
! 	    gen_op_addl_T0_T1(); /* GR[b] += dx */
  	    gen_movl_reg_T1(b);
  	    gen_op_copy_T0_T2(); /* offset = GR[b] */
***************
*** 897,901 ****
  	default:
  	    gen_movl_T1_reg(b);
! 	    gen_op_addl_T0_T1(); /* offset = GR[b] + dx */
  	    break;
      }
--- 897,901 ----
  	default:
  	    gen_movl_T1_reg(b);
! 	    gen_op_addl_T1_T0(); /* offset = GR[b] + dx */
  	    break;
      }
***************
*** 1210,1215 ****
              ext6 = field(insn, 6, 6);
              t = field(insn, 0, 5);
!             gen_movl_reg_T0(r1);
!             gen_movl_reg_T1(r2);
  
              /* Opcode Extensions */
--- 1210,1215 ----
              ext6 = field(insn, 6, 6);
              t = field(insn, 0, 5);
!             gen_movl_T0_reg(r1);
!             gen_movl_T1_reg(r2);
  
              /* Opcode Extensions */
***************
*** 1219,1223 ****
                      break;
                  case 0x38: /* ADDO */
!                     gen_op_movl_T0_T2();
                      gen_op_addo_T1_T0();
                      /* if sign(T0) != sign(T1) &&
--- 1219,1223 ----
                      break;
                  case 0x38: /* ADDO */
!                     gen_op_copy_T2_T0();
                      gen_op_addo_T1_T0();
                      /* if sign(T0) != sign(T1) &&
***************
*** 1296,1300 ****
                  case 0x26: /* UADDCM */
                      gen_op_com_T1();
!                     gen_op_addl_T0_T1();
                      break;
                  case 0x27: /* UADDCMT */
--- 1296,1300 ----
                  case 0x26: /* UADDCM */
                      gen_op_com_T1();
!                     gen_op_addl_T1_T0();
                      break;
                  case 0x27: /* UADDCMT */
***************
*** 1302,1318 ****
                      break;
                  case 0x28: /* ADDL */
!                     gen_op_addl_T0_T1();
                      break;
                  case 0x29: /* SH1ADDL */
                      gen_shift_T0(1);
!                     gen_op_addl_T0_T1();
                      break;
                  case 0x2A: /* SH2ADDL */
                      gen_shift_T0(2);
!                     gen_op_addl_T0_T1();
                      break;
                  case 0x2B: /* SH3ADDL */
                      gen_shift_T0(3);
!                     gen_op_addl_T0_T1();
                      break;
                  case 0x2E: /* DCOR */
--- 1302,1318 ----
                      break;
                  case 0x28: /* ADDL */
!                     gen_op_addl_T1_T0();
                      break;
                  case 0x29: /* SH1ADDL */
                      gen_shift_T0(1);
!                     gen_op_addl_T1_T0();
                      break;
                  case 0x2A: /* SH2ADDL */
                      gen_shift_T0(2);
!                     gen_op_addl_T1_T0();
                      break;
                  case 0x2B: /* SH3ADDL */
                      gen_shift_T0(3);
!                     gen_op_addl_T1_T0();
                      break;
                  case 0x2E: /* DCOR */
***************
*** 1336,1340 ****
                      break;
              }
!             gen_movl_T0_reg(t);
              break;
          }
--- 1336,1340 ----
                      break;
              }
!             gen_movl_reg_T0(t);
              break;
          }
***************
*** 1694,1701 ****
              switch(ext3) {
                  case 0: /* BL */
!                     /* generate (iaoq_next <- iaoq_front + disp + 8) */
! 		    gen_branch(dc, 0, dc->iaoq[0] + disp + 8, dc->iaoq[0] + disp + 12);
!                     /* generate (copy iaoq_back + 4 into t) */
!                     /* if (n) generate (psw |= PSW_N); */
                      break;
                  case 2: /* BLR */
--- 1694,1703 ----
              switch(ext3) {
                  case 0: /* BL */
!                     /* TODO: dc->iaoq[1] + 4 into t */
!                     if (n) {
!                         gen_branch(dc, 0, dc->iaoq[0] + disp + 8, dc->iaoq[0] + disp + 12);
!                     } else {
!                         gen_branch(dc, 0, dc->iaoq[1], dc->iaoq[0] + disp + 8);
!                     }
                      break;
                  case 2: /* BLR */

Index: op.c
===================================================================
RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v
retrieving revision 1.14
retrieving revision 1.15
diff -C2 -d -r1.14 -r1.15
*** op.c	12 Mar 2007 14:27:29 -0000	1.14
--- op.c	12 Mar 2007 15:50:26 -0000	1.15
***************
*** 499,503 ****
  
  /* add logical */
! void OPPROTO op_addl_T0_T1(void)
  {
      T0 += T1;
--- 499,503 ----
  
  /* add logical */
! void OPPROTO op_addl_T1_T0(void)
  {
      T0 += T1;
***************
*** 505,514 ****
  }
  
! void OPPROTO op_addl_T1_T0(void)
  {
      T1 += T0;
  }
  
! void OPPROTO op_addl_T1_T2(void)
  {
      T1 += T2;
--- 505,514 ----
  }
  
! void OPPROTO op_addl_T0_T1(void)
  {
      T1 += T0;
  }
  
! void OPPROTO op_addl_T2_T1(void)
  {
      T1 += T2;
***************
*** 572,580 ****
  }
  
- void OPPROTO op_movl_T0_T2(void)
- {
-     /* XXX */
- }
- 
  void OPPROTO op_addo_T1_T0(void)
  {
--- 572,575 ----