The HDL Complexity Tool / News: Recent posts

In the upcoming release, we will introduce the interactive shell! This feature will be available by default for interactive sessions with the HCT, but scripts will continue to be able to use command arguments. The benefit of the interactive shell include: an easy to use interface, specialized HCT commands, access to typical BASH shell commands and of course persistence of state determined by input commands. The shell simplifies the interaction between the user and the HCT, thus minimizing the "complexity" of user interaction ;)

In the upcoming release, we will introduce module hierarchy graphics! This allows users to visualize a design's module instantiation hierarchy in a tree-like format. All of the currently supported HDLs will be able to take advantage of this feature.

We are proud to announce beta **VHDL** support! The VHDL parser is bug free and feature complete, but we need your help to give it a thorough work out. Additionally, we have improved the quality of the installation process to make it easier to install on Linux, Windows and Mac.

Announcing the HCT version 0.7.50 release!!! This release fully supports Verilog and Cyclicity CDL, with experimental VHDL support. Our new configuration system makes it much easier to install the HCT on Windows, Mac and Linux workstations. The parser engine's performance is significantly improved. Various bug fixes are implemented, most notably correcting flaws in the SLOC and Lines of Comments metrics. Our project file hierarchy is restructured and finalized.... read more

We've numerous requests to implement VHDL in the HCT. So alright, we'll do it ;)

We're currently planning a VHDL parser module to complement the existing Verilog and CDL parsers. We plan to release a beta version within the next 2 to 3 months.

Want it faster? Then please donate your time to give us a hand!

This release is the final fully modified version of the tool. From this point on, we expect to simply add to the existing functionality.

In this version we support only Verilog, but the CDL language will be coming soon. In the upcoming version, we will extend the API documentation as well as include instructions on how to add a new language of your own.

The HCT project has grown, so we need your help! Please email us today if you are interested in joining this exciting project.

The HDL Complexity Tool parses large complex hardware projects' source code to produce useful complexity results. GOALS: 1)Practical, effective and simple 2) Integrates with existing design flows 3) Used on real projects 4) Based on existing research

This is a completely redesigned tool that produces stable complexity metrics from Verilog and Cyclicity CDL projects. Mixed code is not a problem and both files and modules are supported. We have focused on useful complexity metrics in several output formats and tried to improve performance as well. This release has been fielded and we are gathering feedback. Please join this alpha deployment stage and let us know what you need.

Now, not only software engineers can enjoy the benefits of complexity analysis! The HDL Complexity Tool applies state of the art complexity analysis to complex hardware designs. The 0.0.1 release is an early alpha release targeting Verilog and Cyclicity CDL. Our team members continue to develop the practical aspects of complexity analysis using this and future versions of HCT on real world projects. Do you want to help up meet our goal of an EFFECTIVE open source complexity analysis tool for your design flow? Then please give it a try and let us know what you think!