[Hackndev-commit] SF.net SVN: hackndev: [1291] linux4palm/linux/trunk

[<mar...@us...>]

Revision: 1291
          http://hackndev.svn.sourceforge.net/hackndev/?rev=1291&view=rev
Author:   marex_z71
Date:     2007-08-31 13:26:04 -0700 (Fri, 31 Aug 2007)

Log Message:
-----------
PalmTX: added RnB GPIO and fixed memory freeing if something breaks

Modified Paths:
--------------
    linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c
    linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h

Modified: linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c
===================================================================
--- linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c	2007-08-30 02:41:10 UTC (rev 1290)
+++ linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c	2007-08-31 20:26:04 UTC (rev 1291)
@@ -82,6 +82,11 @@
 	}
 }
 
+static int palmtx_device_ready(struct mtd_info *mtd)
+{
+	return GET_PALMTX_GPIO(NAND_READY);
+}
+
 /*
  * Main initialization routine
  */
@@ -143,8 +148,7 @@
 	this->IO_ADDR_R = nandaddr;
 	this->IO_ADDR_W = nandaddr;
 	this->cmd_ctrl = palmtx_hwcontrol;
-	/* For the time being ... */
-	this->dev_ready = NULL;
+	this->dev_ready = palmtx_device_ready;
 	/* 15 us command delay time */
 	this->chip_delay = 15;
 	this->ecc.mode = NAND_ECC_SOFT;
@@ -154,7 +158,10 @@
 	if (nand_scan(palmtx_nand_mtd, 1)) {
 		printk(KERN_NOTICE "No NAND device - returning -ENXIO\n");
 		kfree(palmtx_nand_mtd);
+		iounmap((void *)palmtx_nand_mtd);
 		iounmap((void *)nandaddr);
+		iounmap((void *)nand_ale);
+		iounmap((void *)nand_cle);
 		return -ENXIO;
 	}
 #ifdef CONFIG_MTD_CMDLINE_PARTS

Modified: linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h
===================================================================
--- linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h	2007-08-30 02:41:10 UTC (rev 1290)
+++ linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h	2007-08-31 20:26:04 UTC (rev 1291)
@@ -97,6 +97,7 @@
 
 /* NAND Flash ... these GPIOs are probably incorrect! */
 #define GPIO_NR_PALMTX_NAND_CS1_N		15
+#define GPIO_NR_PALMTX_NAND_READY		18
 #define GPIO_NR_PALMTX_NAND_WE_N		49
 
 /* INTERRUPTS */


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