[Hackndev-commit] SF.net SVN: hackndev: [1286] linux4palm/linux/trunk

[<mar...@us...>]

Revision: 1286
          http://hackndev.svn.sourceforge.net/hackndev/?rev=1286&view=rev
Author:   marex_z71
Date:     2007-08-29 02:55:32 -0700 (Wed, 29 Aug 2007)

Log Message:
-----------
PalmTX: this is how the driver should look like according to snua12s' notes from desolderation of broken palmtx board ... yet it still doesnt work

Modified Paths:
--------------
    linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c
    linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h

Modified: linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c
===================================================================
--- linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c	2007-08-29 02:12:51 UTC (rev 1285)
+++ linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c	2007-08-29 09:55:32 UTC (rev 1286)
@@ -31,19 +31,6 @@
 #include <asm/memory.h>
 #include <asm/mach-types.h>
 
-/* Select the chip by setting nCE to low */
-#define NAND_CTL_SETNCE		1
-/* Deselect the chip by setting nCE to high */
-#define NAND_CTL_CLRNCE		2
-/* Select the command latch by setting CLE to high */
-#define NAND_CTL_SETCLE		3
-/* Deselect the command latch by setting CLE to low */
-#define NAND_CTL_CLRCLE		4
-/* Select the address latch by setting ALE to high */
-#define NAND_CTL_SETALE		5
-/* Deselect the address latch by setting ALE to low */
-#define NAND_CTL_CLRALE		6
-
 /*
  * MTD structure
  */
@@ -74,42 +61,24 @@
 			    unsigned int ctrl)
 {
 	struct nand_chip *chip = mtd->priv;
+	unsigned long bits = 0;
 
         if (ctrl & NAND_CTRL_CHANGE) {
-                switch (cmd) {
-                case NAND_CTL_SETCLE:
-                        SET_PALMTX_GPIO(NAND_CLE,1);
-                        break;
-                case NAND_CTL_CLRCLE:
-                        SET_PALMTX_GPIO(NAND_CLE,0);
-                        break;
-                case NAND_CTL_SETALE:
-                        SET_PALMTX_GPIO(NAND_ALE,1);
-                        break;
-                case NAND_CTL_CLRALE:
-                        SET_PALMTX_GPIO(NAND_ALE,0);
-                        break;
-                case NAND_CTL_SETNCE:
-                        SET_PALMTX_GPIO(NAND_NCE,1);
-                        break;
-                case NAND_CTL_CLRNCE:
-                        SET_PALMTX_GPIO(NAND_NCE,0);
-                        break;
-                }
+	    /* Select chip */
+	    SET_PALMTX_GPIO(NAND_CS1_N, (ctrl & NAND_NCE) ? 0 : 1);
+
+	    /* Set control lines */
+	    if (ctrl & NAND_CLE)
+		bits |= 1<<25;
+	    if (ctrl & NAND_ALE)
+		bits |= 1<<24;
+	    iowrite32(bits, chip->IO_ADDR_W);
         }
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, (void __iomem *)((unsigned long)chip->IO_ADDR_W));
-}
 
-/*
- * read device ready pin
- */
-#if 0
-static int palmtx_device_ready(struct mtd_info *mtd)
-{
-	return GET_PALMTX_GPIO(NAND_READY);
+	/* If there is a command for the chip, send it */
+        if (cmd != NAND_CMD_NONE)
+	    iowrite32((cmd & 0xff) | bits, chip->IO_ADDR_W);
 }
-#endif
 
 /*
  * Main initialization routine
@@ -125,12 +94,6 @@
 	if (!machine_is_xscale_palmtx())
 		return -ENODEV;
 
-	nandaddr = ioremap(PALMTX_PHYS_NAND_START, 0x1000);
-	if (!nandaddr) {
-		printk("Failed to ioremap NAND flash.\n");
-		return -ENOMEM;
-	}
-
 	/* Allocate memory for MTD device structure and private data */
 	palmtx_nand_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
 	if (!palmtx_nand_mtd) {
@@ -139,6 +102,13 @@
 		return -ENOMEM;
 	}
 
+	/* Remap physical address of flash */
+	nandaddr = ioremap(PALMTX_PHYS_NAND_START, 0x1000);
+	if (!nandaddr) {
+		printk("Failed to ioremap NAND flash.\n");
+		return -ENOMEM;
+	}
+
 	/* Get pointer to private data */
 	this = (struct nand_chip *)(&palmtx_nand_mtd[1]);
 
@@ -150,24 +120,14 @@
 	palmtx_nand_mtd->priv = this;
 	palmtx_nand_mtd->owner = THIS_MODULE;
 
-	/*
-	 * Enable VPEN ... isnt it on all the time?
-	 */
-#if 0
-	SET_PALMTX_GPIO(NAND_POWER, 1);
-#endif
-
 	/* insert callbacks */
 	this->IO_ADDR_R = nandaddr;
 	this->IO_ADDR_W = nandaddr;
 	this->cmd_ctrl = palmtx_hwcontrol;
-#if 0
-	this->dev_ready = palmtx_device_ready;
-#else
+	/* For the time being ... */
 	this->dev_ready = NULL;
-#endif
 	/* 15 us command delay time */
-	this->chip_delay = 50;
+	this->chip_delay = 15;
 	this->ecc.mode = NAND_ECC_SOFT;
 	this->options = NAND_NO_AUTOINCR;
 

Modified: linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h
===================================================================
--- linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h	2007-08-29 02:12:51 UTC (rev 1285)
+++ linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h	2007-08-29 09:55:32 UTC (rev 1286)
@@ -96,13 +96,9 @@
 #define GPIO_NR_PALMTX_PCMCIA_READY		116
 
 /* NAND Flash ... these GPIOs are probably incorrect! */
-#define GPIO_NR_PALMTX_NAND_POWER		19
-#define GPIO_NR_PALMTX_NAND_READY		115
-#define GPIO_NR_PALMTX_NAND_CLE			79
-#define GPIO_NR_PALMTX_NAND_ALE			113
-#define GPIO_NR_PALMTX_NAND_NCE			114
+#define GPIO_NR_PALMTX_NAND_CS1_N		15
+#define GPIO_NR_PALMTX_NAND_WE_N		49
 
-
 /* INTERRUPTS */
 
 #define IRQ_GPIO_PALMTX_SD_DETECT_N     	IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N)


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