From: <bob...@us...> - 2007-07-13 11:32:28
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Revision: 1136 http://svn.sourceforge.net/hackndev/?rev=1136&view=rev Author: bobofdoom Date: 2007-07-13 04:32:23 -0700 (Fri, 13 Jul 2007) Log Message: ----------- Cocoboot: Integrated treo code (removed all ifdefs). Closes: 5 This commit adjusts the boot procedure to disable all memory protection. This means that we do not need to make a writable copy of translation table on treo devices anymore. All treo #ifdefs have been removed and the translation table base setting has been moved to mach.c as a runtime check. Modified Paths: -------------- cocoboot/trunk/Changelog cocoboot/trunk/Makefile cocoboot/trunk/arm/arm.c cocoboot/trunk/arm/boot.c cocoboot/trunk/include/arm.h cocoboot/trunk/include/cocoboot.h cocoboot/trunk/include/shared.h cocoboot/trunk/m68k/cocoboot.c cocoboot/trunk/m68k/mach.c cocoboot/trunk/m68k/mainform.c cocoboot/trunk/m68k/mem.c Modified: cocoboot/trunk/Changelog =================================================================== --- cocoboot/trunk/Changelog 2007-07-13 10:29:13 UTC (rev 1135) +++ cocoboot/trunk/Changelog 2007-07-13 11:32:23 UTC (rev 1136) @@ -1,3 +1,4 @@ + - Cleaned up treo code (removed all #ifdefs) - Removed kernel relocation for speed and reliability (suggested by phire) - Added simple USB console. Modified: cocoboot/trunk/Makefile =================================================================== --- cocoboot/trunk/Makefile 2007-07-13 10:29:13 UTC (rev 1135) +++ cocoboot/trunk/Makefile 2007-07-13 11:32:23 UTC (rev 1136) @@ -12,7 +12,7 @@ all: cocoboot.prc install: cocoboot.prc - pilot-xfer -p /dev/tts/USB0 -i cocoboot.prc + pilot-xfer -p /dev/ttyUSB1 -i cocoboot.prc cocoboot.prc: arm-objs m68k-objs gui iTbl.bin build-prc -n Cocoboot -c CcBt $(EXECS) *.bin Modified: cocoboot/trunk/arm/arm.c =================================================================== --- cocoboot/trunk/arm/arm.c 2007-07-13 10:29:13 UTC (rev 1135) +++ cocoboot/trunk/arm/arm.c 2007-07-13 11:32:23 UTC (rev 1136) @@ -264,16 +264,9 @@ phys = (fld & 0xfff00000) | (virt & 0x000fffff); } else if ((fld & FLD_MASK) == FLD_COARSE) { /* 2nd level, yuck. Here's hoping we can access it. */ -#ifdef TREO650 - /*Treo 650 tables are in a peice of memory in a 1:1 - *mapping*/ sld_p = (UInt32*) ( ((fld & 0xFFFFFc00) | - ((virt & 0xfF000) >> 10))); -#else - sld_p = (UInt32*) ( ((fld & 0xFFFFFc00) | ((virt & 0xfF000) >> 10)) - - g->ram_base); -#endif + - g->tt_offset); sld = *sld_p; /* crash? */ if((sld & 3) == 2) { /* small page */ phys = (sld & 0xFFFFF000) | (virt & 0xFFF); @@ -285,16 +278,9 @@ } else { /* FIXME: THIS IS WRONG!! */ /* 2nd level, yuck. Here's hoping we can access it. */ -#ifdef TREO650 - /*Treo 650 tables are in a peice of memory in a 1:1 - *mapping*/ sld_p = (UInt32*) ( ((fld & 0xFFFFF000) | - ((virt & 0xff000) >> 10))); -#else - sld_p = (UInt32*) ( ((fld & 0xFFFFF000) | ((virt & 0xff000) >> 10)) - - g->ram_base); -#endif + - g->tt_offset); sld = *sld_p; /* crash? */ if((sld & 3) == 2) { /* small page */ phys = (sld & 0xFFFFF000) | (virt & 0xFFF); @@ -334,13 +320,7 @@ UInt32 map_mem(ArmGlobals *g, UInt32 phys) { -#ifdef TREO650 - /*The treo650 ttb is mapped read only, so we have to modify - *a copy*/ - UInt32 *tt = (UInt32*) g->new_vttb; -#else UInt32 *tt = (UInt32*) g->vttb; -#endif UInt32 i, rec; UInt32 va; @@ -363,89 +343,10 @@ return NULL; } -#ifdef TREO650 -/* The treo650 ttb is in a 1:1 mapping, but cruically it's Readonly - * we still have access to the TTB registers though as we're in System - * mode, so we copy the current TTB to a buffer - * and then we can modify that, this code copies the ttb and then - * switches the mmu to the new copy - */ -void copy_map_and_switch(ArmGlobals *g) -{ - UInt32 *src=(UInt32 *) g->vttb; - UInt32 *dst=(UInt32 *) g->new_vttb; - UInt32 ttbr0; - int i; - - - for (i=0;i<4096;++i) { - dst[i]=src[i]; - } - - asm("mrc p15, 0, r0, c2, c0, 0\nmov %0, r0": "=r"(ttbr0): :"r0"); - - - ttbr0&=0x1fUL; - ttbr0|=g->new_pttb; - - asm volatile ( "mov r0, %0\n" - "mcr p15, 0, r0, c2, c0, 0" - : - : "r"(ttbr0) - : "r0" ); - - - /* invalidate TLB */ - asm volatile ("mov r0, #0"); - asm volatile ("mcr p15, 0, r0, c8, c7, 0"); - - CPWAIT - - - for(i=0; i<100000; i++); - - -} - -/* Restore the MMU to look at the palmos TTB */ -void restore_map(ArmGlobals *g) -{ - UInt32 ttbr0; - int i; - - asm("mrc p15, 0, r0, c2, c0, 0\nmov %0, r0": "=r"(ttbr0): :"r0"); - - ttbr0&=0x1fUL; - ttbr0|=g->pttb; - - asm volatile ( "mov r0, %0\n" - "mcr p15, 0, r0, c2, c0, 0" - : - : "r"(ttbr0) - : "r0" ); - - - /* invalidate TLB */ - asm volatile ("mov r0, #0"); - asm volatile ("mcr p15, 0, r0, c8, c7, 0"); - - CPWAIT - - for(i=0; i<100000; i++); -} -#endif - void map(ArmGlobals *g, UInt32 phys, UInt32 virt) { int i; -#ifdef TREO650 - /*On the treo650 use the copy of the ttb, not the real - *ttb which is read only - */ - UInt32 *tt = (UInt32*) g->new_vttb; -#else UInt32 *tt = (UInt32*) g->vttb; -#endif UInt32 idx = virt >> 20; tt[idx] = (phys & 0xFFF00000) | 0xc1a; Modified: cocoboot/trunk/arm/boot.c =================================================================== --- cocoboot/trunk/arm/boot.c 2007-07-13 10:29:13 UTC (rev 1135) +++ cocoboot/trunk/arm/boot.c 2007-07-13 11:32:23 UTC (rev 1136) @@ -23,17 +23,12 @@ #define MACH_TYPE_T3XSCALE 829 -#ifdef TREO650 #define TAG_OFFSET 0x100 -#define INITRD_OFFSET 0x1500000 -#else -#define TAG_OFFSET 0x100 #define INITRD_OFFSET 0x0400000 -#endif #define T3_INITRD_OFFSET 0x1500000 -static void jump_to_kernel(UInt32 kernel_base, UInt32 tag_base, UInt32 mach) +static void jump_to_kernel(void *kernel_base, UInt32 tag_base, UInt32 mach) { asm volatile ( "mov r0, #0\n" "mov r1, %0\n" /* mach id */ @@ -98,10 +93,6 @@ kernel = (void *)virt_to_phys(g, (UInt32) kernel); cmdline = (char *)virt_to_phys(g, (UInt32) cmdline); -#ifdef TREO650 - g->new_pttb=virt_to_phys(g,g->new_vttb); -#endif - if(initrd) initrd = (void *)virt_to_phys(g, (UInt32) initrd); pg = (void *)virt_to_phys(g, (UInt32) g); @@ -130,18 +121,14 @@ irq_off(); -#ifdef TREO650 - copy_map_and_switch(g); -#endif + /* Disable memory protection (page table is read-only on treos) */ + asm volatile ("mcr p15, 0, %0, c3, c3, 0" : : "r"(0xffffffff) ); /* Map the page containing pphys_jump to identity */ map(g, (UInt32)pphys_jump, (UInt32)pphys_jump); /* make sure the mapping worked */ if(*(UInt32*)(vphys_jump) != *(UInt32*)(pphys_jump)) { -#ifdef TREO650 - restore_map(g); -#endif irq_on(); return 0xc01d; } @@ -184,14 +171,10 @@ #ifdef MOVE_FRAMEBUFFER map_lcd(); #endif -#ifdef TREO650 - setup_treo650_cpu(); -#else /* do CPU-specific configuration (like interrupt masking) */ if (pg->cpu & CPUV_INTEL) { setup_xscale_cpu(); } -#endif if (pg->mach_num==MACH_TYPE_T3XSCALE){ initrd_offset=T3_INITRD_OFFSET; Modified: cocoboot/trunk/include/arm.h =================================================================== --- cocoboot/trunk/include/arm.h 2007-07-13 10:29:13 UTC (rev 1135) +++ cocoboot/trunk/include/arm.h 2007-07-13 11:32:23 UTC (rev 1136) @@ -9,16 +9,7 @@ UInt32 virt_to_phys(ArmGlobals *g, UInt32 virt); void map(ArmGlobals *g, UInt32 phys, UInt32 virt); -#ifdef TREO650 -void copy_map_and_switch(ArmGlobals *g); -void restore_map(ArmGlobals *g); -#endif - - -#ifdef TREO650 /*cpu.c*/ -void setup_treo650_cpu(void); -#endif void setup_xscale_cpu(void); /* boot.c */ Modified: cocoboot/trunk/include/cocoboot.h =================================================================== --- cocoboot/trunk/include/cocoboot.h 2007-07-13 10:29:13 UTC (rev 1135) +++ cocoboot/trunk/include/cocoboot.h 2007-07-13 11:32:23 UTC (rev 1136) @@ -10,6 +10,7 @@ void lprintf (const char *template, ...); UInt32 call_arm(ArmStack *stack, UInt32 func); +UInt32 get_tt_offset(); UInt32 get_linux_mach_id(); char *get_mach_name(); void SetFieldTextFromStr(FieldPtr fldP, char *strP, Boolean redraw); Modified: cocoboot/trunk/include/shared.h =================================================================== --- cocoboot/trunk/include/shared.h 2007-07-13 10:29:13 UTC (rev 1135) +++ cocoboot/trunk/include/shared.h 2007-07-13 11:32:23 UTC (rev 1136) @@ -26,15 +26,16 @@ UInt32 pttb; UInt32 vttb; - UInt32 new_vttb; - UInt32 new_pttb; - UInt32 cpu; + UInt32 tt_offset; + UInt32 ram_base; UInt32 ram_size; UInt32 mach_num; + + UInt32 pad[4]; } ArmGlobals; void push_uint32(ArmStack *stack, UInt32 n); Modified: cocoboot/trunk/m68k/cocoboot.c =================================================================== --- cocoboot/trunk/m68k/cocoboot.c 2007-07-13 10:29:13 UTC (rev 1135) +++ cocoboot/trunk/m68k/cocoboot.c 2007-07-13 11:32:23 UTC (rev 1136) @@ -130,6 +130,7 @@ arm_globals.ram_base = EndianFix32(get_ram_base()); arm_globals.ram_size = EndianFix32(get_ram_size()); arm_globals.mach_num = EndianFix32(835); + arm_globals.tt_offset = get_tt_offset(); } /** Modified: cocoboot/trunk/m68k/mach.c =================================================================== --- cocoboot/trunk/m68k/mach.c 2007-07-13 10:29:13 UTC (rev 1135) +++ cocoboot/trunk/m68k/mach.c 2007-07-13 11:32:23 UTC (rev 1136) @@ -16,6 +16,7 @@ */ #include <PalmOS.h> +#include "mem.h" struct Machine { UInt32 palmos_id; @@ -81,3 +82,21 @@ check_mach(); return mach_table[mach].name; } + +/** + * Offset to subtract from translation table entries. + * On treo's translation table is 1:1 mapped so this is zero. + * On other devices the translation table stuff starts at 0x0 so we + * subtract ram_base. + */ +UInt32 get_tt_offset() +{ + check_mach(); + switch (mach_table[mach].linux_id) { + case 909: /* Treo 650 */ + case 1230: /* Treo 680 */ + return 0; + default: + return get_ram_base(); + } +} Modified: cocoboot/trunk/m68k/mainform.c =================================================================== --- cocoboot/trunk/m68k/mainform.c 2007-07-13 10:29:13 UTC (rev 1135) +++ cocoboot/trunk/m68k/mainform.c 2007-07-13 11:32:23 UTC (rev 1136) @@ -262,48 +262,19 @@ if(!use_initrd || initrd_size) { cmdline = read_command_line(); - //PrefSetAppPreferences ('CcBt', 1, 0, cmdline, 256, true); - //lprintf("Fare thee well 68k world!\n"); - arm_globals.mach_num = EndianFix32(read_mach_id()); -#ifdef TREO650 - { - extern void *MemGluePtrNew(UInt32); - void *ttb=NULL; - UInt32 ttb_aligned; - - ret=65536UL; - ttb=MemGluePtrNew(ret); - - ttb_aligned=(UInt32)ttb; - ttb_aligned+=(UInt32) 16383; - ttb_aligned&=~(UInt32) 16383; - - arm_globals.new_vttb = EndianFix32(ttb_aligned); - } -#endif - push_uint32(arm_stack, (UInt32)cmdline); push_uint32(arm_stack, initrd_size); push_uint32(arm_stack, (UInt32)initrd); push_uint32(arm_stack, kernel_size); push_uint32(arm_stack, (UInt32)kernel); - ret = call_arm(arm_stack, ARM_boot_linux); /* we're back?! Boot must have failed. */ lprintf("Returned: %lx\n", ret); -#if 0 - { - char msg[1024]; - sprintf(msg, "0x%08lx, 0x%08lx, 0x%08lx", ret,(UInt32) ttb, ttb_aligned); - FrmCustomAlert(InfoAlert, "result:", msg, " "); - } -#endif - } if (initrd_size) FtrPtrFree(CREATOR_ID, FEATURE_NUM + 1); @@ -311,7 +282,6 @@ if (kernel_size) FtrPtrFree(CREATOR_ID, FEATURE_NUM); - //lprintf("Boot aborted.\n"); } Boolean mainform_menu_event(Int16 id) Modified: cocoboot/trunk/m68k/mem.c =================================================================== --- cocoboot/trunk/m68k/mem.c 2007-07-13 10:29:13 UTC (rev 1135) +++ cocoboot/trunk/m68k/mem.c 2007-07-13 11:32:23 UTC (rev 1136) @@ -81,11 +81,7 @@ /* FIXME: Hack alert. We're making an assumption about where PalmOS maps the first part of RAM.. * Is there a better way of doing this? we'll need to hardcode the value for T|T2 */ -#ifdef TREO650 - return get_ttb(); -#else - return get_ttb() - get_ram_base(); -#endif + return get_ttb() - get_tt_offset(); } UInt32 virt_to_phys(UInt32 virt) This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site. |