Menu
▾
▴
[Hackndev-commit] SF.net SVN: hackndev: [623] linux4palm/linux/trunk
|
From: <hap...@us...> - 2006-10-12 17:48:30
|
Revision: 623
http://svn.sourceforge.net/hackndev/?rev=623&view=rev
Author: happy-slapin
Date: 2006-10-12 10:48:14 -0700 (Thu, 12 Oct 2006)
Log Message:
-----------
zire72: Found LED GPIO, used as debugging.
zire72: Finzlly fixed support for keypad. Now it really works.
zire72: updated GPIO map in SVN for proper awk parsing.
ALL: semi-applied PXA27 udc-ep and overlays patches from OpenZaurus
Modified Paths:
--------------
linux4palm/linux/trunk/arch/arm/configs/palmz72_defconfig
linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/Kconfig
linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/gpio_map.txt
linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/palmz72.c
linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmz72-gpio.h
linux4palm/linux/trunk/include/asm-arm/arch-pxa/pxa-regs.h
Modified: linux4palm/linux/trunk/arch/arm/configs/palmz72_defconfig
===================================================================
--- linux4palm/linux/trunk/arch/arm/configs/palmz72_defconfig 2006-10-06 17:50:43 UTC (rev 622)
+++ linux4palm/linux/trunk/arch/arm/configs/palmz72_defconfig 2006-10-12 17:48:14 UTC (rev 623)
@@ -1,13 +1,15 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.16-hnd0
-# Thu Sep 28 19:45:51 2006
+# Linux kernel version: 2.6.17-hnd0
+# Thu Oct 12 20:26:28 2006
#
CONFIG_ARM=y
CONFIG_MMU=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
#
# Code maturity level options
@@ -22,14 +24,16 @@
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
-# CONFIG_SWAP is not set
-# CONFIG_SYSVIPC is not set
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_SYSCTL is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
# CONFIG_MINIMAL_OOPS is not set
+# CONFIG_RELAY is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_UID16=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -43,15 +47,11 @@
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
-# CONFIG_SHMEM is not set
+CONFIG_SHMEM=y
CONFIG_USELIB=y
# CONFIG_CORE_DUMP is not set
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
CONFIG_SLAB=y
-CONFIG_TINY_SHMEM=y
+# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
@@ -61,7 +61,6 @@
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_OBSOLETE_MODPARM=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
@@ -69,6 +68,7 @@
#
# Block layer
#
+# CONFIG_BLK_DEV_IO_TRACE is not set
#
# IO Schedulers
@@ -76,7 +76,7 @@
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
+CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
@@ -90,11 +90,13 @@
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_IOP3XX is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_L7200 is not set
CONFIG_ARCH_PXA=y
# CONFIG_ARCH_RPC is not set
@@ -114,6 +116,7 @@
# Intel PXA2xx Implementations
#
# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
# CONFIG_MACH_MAINSTONE is not set
# CONFIG_ARCH_PXA_IDP is not set
# CONFIG_ARCH_ESERIES is not set
@@ -127,6 +130,12 @@
# CONFIG_MACH_HX2750 is not set
# CONFIG_ARCH_H5400 is not set
# CONFIG_MACH_HIMALAYA is not set
+# CONFIG_MACH_HTCUNIVERSAL is not set
+# CONFIG_MACH_HTCALPINE is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_HTCAPACHE is not set
+# CONFIG_MACH_BLUEANGEL is not set
+# CONFIG_MACH_HTCBEETLES is not set
# CONFIG_ARCH_AXIMX5 is not set
# CONFIG_ARCH_AXIMX3 is not set
# CONFIG_ARCH_ROVERP1 is not set
@@ -137,10 +146,10 @@
# CONFIG_MACH_XSCALE_PALMTT5 is not set
# CONFIG_MACH_XSCALE_PALMTX is not set
CONFIG_MACH_PALMZ72=y
-CONFIG_PALMZ72_BUTTONS=y
# CONFIG_MACH_OMAP_PALMTC is not set
# CONFIG_PXA_SHARPSL is not set
CONFIG_PXA27x=y
+CONFIG_PXA_RTC_EPOCH=1970
# CONFIG_SA1100_H3100 is not set
# CONFIG_SA1100_H3600 is not set
# CONFIG_SA1100_H3800 is not set
@@ -166,6 +175,7 @@
CONFIG_ARM_THUMB=y
# CONFIG_ARMBOOT_PROC is not set
CONFIG_XSCALE_PMU=y
+# CONFIG_KEXEC is not set
#
# Compaq/iPAQ Platforms
@@ -194,8 +204,8 @@
#
CONFIG_PREEMPT=y
# CONFIG_NO_IDLE_HZ is not set
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
@@ -228,7 +238,7 @@
# At least one emulation must be selected
#
CONFIG_FPE_NWFPE=y
-CONFIG_FPE_NWFPE_XP=y
+# CONFIG_FPE_NWFPE_XP is not set
# CONFIG_FPE_FASTFPE is not set
#
@@ -237,6 +247,7 @@
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
#
# Power management options
@@ -268,12 +279,15 @@
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_BIC=y
# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETFILTER is not set
#
@@ -365,7 +379,13 @@
#
# CONFIG_BT_HCIUART is not set
# CONFIG_BT_HCIVHCI is not set
-# CONFIG_IEEE80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+# CONFIG_IEEE80211_CRYPT_WEP is not set
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+CONFIG_WIRELESS_EXT=y
#
# Device Drivers
@@ -404,9 +424,7 @@
CONFIG_BLK_DEV_LOOP=m
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_RAM is not set
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
@@ -517,10 +535,19 @@
#
# Input Device Drivers
#
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_PXA27x=y
+# CONFIG_KEYBOARD_PALMIR is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
@@ -536,7 +563,10 @@
#
# Hardware I/O ports
#
-# CONFIG_SERIO is not set
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
@@ -607,10 +637,20 @@
#
# SPI support
#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_PXA2XX=m
+
+#
+# SPI Protocol Masters
+#
+
+#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
@@ -642,13 +682,23 @@
# CONFIG_MCP is not set
#
-# Multimedia Capabilities Port drivers
+# LED devices
#
+# CONFIG_NEW_LEDS is not set
#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
+CONFIG_VIDEO_V4L2=y
#
# Digital Video Broadcasting Devices
@@ -663,6 +713,7 @@
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_MACMODES is not set
+CONFIG_FB_FIRMWARE_EDID=y
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
# CONFIG_FB_IMAGEON is not set
@@ -697,7 +748,7 @@
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_DEVICE=y
-CONFIG_BACKLIGHT_PALMZ72=y
+# CONFIG_BACKLIGHT_CORGI is not set
CONFIG_BACKLIGHT_PXAPWM=y
# CONFIG_LCD_CLASS_DEVICE is not set
@@ -716,8 +767,10 @@
CONFIG_SND_OSSEMUL=y
# CONFIG_SND_MIXER_OSS is not set
CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
CONFIG_SND_VERBOSE_PRINTK=y
# CONFIG_SND_DEBUG is not set
@@ -748,6 +801,7 @@
#
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
#
@@ -769,6 +823,7 @@
# CONFIG_USB_GADGET_MQ11XX is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_GADGET_DUALSPEED is not set
# CONFIG_USB_ZERO is not set
@@ -782,7 +837,7 @@
#
# MMC/SD Card support
#
-CONFIG_MMC=y
+CONFIG_MMC=m
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_BLOCK=m
CONFIG_MMC_PXA=m
@@ -792,11 +847,26 @@
# CONFIG_MMC_WBSD_PALMT3 is not set
#
-# LED devices
+# Real Time Clock
#
-# CONFIG_CLASS_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=m
#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=m
+CONFIG_RTC_INTF_PROC=m
+CONFIG_RTC_INTF_DEV=m
+
+#
+# RTC drivers
+#
+# CONFIG_RTC_DRV_M48T86 is not set
+CONFIG_RTC_DRV_SA1100=m
+# CONFIG_RTC_DRV_TEST is not set
+
+#
# File systems
#
CONFIG_EXT2_FS=m
@@ -841,7 +911,6 @@
CONFIG_TMPFS=y
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
# CONFIG_CONFIGFS_FS is not set
#
@@ -902,7 +971,7 @@
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
+CONFIG_NLS_CODEPAGE_866=m
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
@@ -924,7 +993,7 @@
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
+CONFIG_NLS_KOI8_R=m
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=m
@@ -942,7 +1011,9 @@
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_FS is not set
CONFIG_FRAME_POINTER=y
+# CONFIG_UNWIND_INFO is not set
# CONFIG_DEBUG_USER is not set
#
Modified: linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/Kconfig
===================================================================
--- linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/Kconfig 2006-10-06 17:50:43 UTC (rev 622)
+++ linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/Kconfig 2006-10-12 17:48:14 UTC (rev 623)
@@ -1,5 +1,6 @@
menuconfig MACH_PALMZ72
bool "Palm Zire 72"
select PXA27x
+ select KEYBOARD_PXA27x
help
This enables support for Palm Zire 72 handheld.
Modified: linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/gpio_map.txt
===================================================================
--- linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/gpio_map.txt 2006-10-06 17:50:43 UTC (rev 622)
+++ linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/gpio_map.txt 2006-10-12 17:48:14 UTC (rev 623)
@@ -1,104 +1,104 @@
GPIO pin Level Dir Function
-GPIO 0 0 I 00
-GPIO 1 1 I 00
-GPIO 2 1 O 00
-GPIO 3 1 O 00
-GPIO 4 1 O 00
-GPIO 5 1 I 00
-GPIO 6 1 I 00
-GPIO 7 1 I 00
-GPIO 8 1 I 00
-GPIO 9 0 I 00
-GPIO 10 1 I 00
-GPIO 11 0 I 00
-GPIO 12 1 I 00
-GPIO 13 0 I 02 KP_DKIN7 // ???
-GPIO 14 0 I 00
-GPIO 15 0 I 00
-GPIO 16 1 O 02 PWM_OUT0
-GPIO 17 1 O 00
-GPIO 18 0 O 00
-GPIO 19 1 O 00
-GPIO 20 1 O 00
-GPIO 21 0 O 00
-GPIO 22 0 O 00
-GPIO 23 0 O 02 SSPSCLK
-GPIO 24 1 O 02 SSPSFRM
-GPIO 25 0 O 02 SSPSTXD
-GPIO 26 1 I 01
-GPIO 27 0 I 00
-GPIO 28 0 I 01 AC97_BITCLK // AC97
-GPIO 29 0 I 01 AC97_SDATA_IN0 // AC97
-GPIO 30 0 O 02 AC97_SDATA_OUT // AC97
-GPIO 31 0 O 02 AC97_SYNC // AC97
-GPIO 32 0 O 00
-GPIO 33 0 O 00
-GPIO 34 1 I 00
-GPIO 35 1 I 01 FFCTS
-GPIO 36 1 O 00
-GPIO 37 1 I 00
-GPIO 38 0 O 00
-GPIO 39 0 O 00
-GPIO 40 0 O 00
-GPIO 41 1 O 02 KP_MKOUT7 // ??
-GPIO 42 1 I 01 IrDA
-GPIO 43 1 O 02 IrDA
-GPIO 44 1 I 01 BTCTS // blutooth
-GPIO 45 1 O 02 BTRTS // blutooth
-GPIO 46 1 I 02 STD_RXD
-GPIO 47 0 O 01 STD_TXD
-GPIO 48 1 I 01 CIF_DD5
-GPIO 49 0 O 00
-GPIO 50 1 I 01 CIF_DD3
-GPIO 51 1 I 01 CIF_DD2
-GPIO 52 1 I 01 CIF_DD4
-GPIO 53 0 O 02 CIF_MCLK
-GPIO 54 1 I 03 CIF_PCLK
-GPIO 55 0 I 01 CIF_DD1
-GPIO 56 1 O 00
-GPIO 57 0 O 00
-GPIO 58 1 O 02 LDD0
-GPIO 59 1 O 02 LDD1
-GPIO 60 1 O 02 LDD2
-GPIO 61 1 O 02 LDD3
-GPIO 62 1 O 02 LDD4
-GPIO 63 1 O 02 LDD5
-GPIO 64 1 O 02 LDD6
-GPIO 65 1 O 02 LDD7
-GPIO 66 1 O 02 LDD8
-GPIO 67 1 O 02 LDD9
-GPIO 68 1 O 02 LDD10
-GPIO 69 1 O 02 LDD11
-GPIO 70 1 O 02 LDD12
-GPIO 71 1 O 02 LDD13
-GPIO 72 1 O 02 LDD14
-GPIO 73 1 O 02 LDD15
-GPIO 74 1 O 02 L_LCLK_RD
-GPIO 75 1 O 02 L_LCLK_A0
-GPIO 76 1 O 02 L_PCLK_WR
-GPIO 77 1 O 02 L_BIAS
-GPIO 78 0 O 00
-GPIO 79 0 O 00
-GPIO 80 1 I 00
-GPIO 81 1 I 02 CIF_DD0
-GPIO 82 0 O 00
-GPIO 83 0 O 00
-GPIO 84 1 I 03 CIF_FV
-GPIO 85 1 I 03 CIF_LV
-GPIO 86 1 I 00
-GPIO 87 0 I 00
-GPIO 88 0 O 00
-GPIO 89 0 O 01 AC97_SYSCLK
-GPIO 90 0 O 00
-GPIO 91 1 O 00
-GPIO 92 0 O 00
-GPIO 93 1 I 02 CIF_DD6
-GPIO 94 0 I 00
-GPIO 95 0 O 00
-GPIO 96 1 O 00
-GPIO 97 0 I 03 KP_MKIN3
-GPIO 98 1 O 00
-GPIO 99 1 I 00
+GPIO_0 0 I 00
+GPIO_1 1 I 00
+GPIO_2 1 O 00 SYS_EN
+GPIO_3 1 O 00
+GPIO_4 1 O 00
+GPIO_5 1 I 00 PWR_CAP<0>
+GPIO_6 1 I 00 PWR_CAP<1>
+GPIO_7 1 I 00 PWR_CAP<2>
+GPIO_8 1 I 00 PWR_CAP<3>
+GPIO_9 0 I 00
+GPIO_10 1 I 00
+GPIO_11 0 I 00
+GPIO_12 1 I 00
+GPIO_13 0 I 02 KP_DKIN7 // ???
+GPIO_14 0 I 00
+GPIO_15 0 I 00 USB_PULLUP
+GPIO_16 1 O 02 PWM_OUT0
+GPIO_17 1 O 00
+GPIO_18 0 O 00
+GPIO_19 1 O 00
+GPIO_20 1 O 00
+GPIO_21 0 O 00
+GPIO_22 0 O 00
+GPIO_23 0 O 02 SSPSCLK
+GPIO_24 1 O 02 SSPSFRM
+GPIO_25 0 O 02 SSPSTXD
+GPIO_26 1 I 01 SSPRXD
+GPIO_27 0 I 00 WM9712_IRQ
+GPIO_28 0 I 01 AC97_BITCLK // AC97
+GPIO_29 0 I 01 AC97_SDATA_IN0 // AC97
+GPIO_30 0 O 02 AC97_SDATA_OUT // AC97
+GPIO_31 0 O 02 AC97_SYNC // AC97
+GPIO_32 0 O 00
+GPIO_33 0 O 00
+GPIO_34 1 I 00
+GPIO_35 1 I 01 FFCTS
+GPIO_36 1 O 00
+GPIO_37 1 I 00
+GPIO_38 0 O 00
+GPIO_39 0 O 00
+GPIO_40 0 O 00
+GPIO_41 1 O 02 KP_MKOUT7 // ??
+GPIO_42 1 I 01 IrDA
+GPIO_43 1 O 02 IrDA
+GPIO_44 1 I 01 BTCTS // blutooth
+GPIO_45 1 O 02 BTRTS // blutooth
+GPIO_46 1 I 02 STD_RXD
+GPIO_47 0 O 01 STD_TXD
+GPIO_48 1 I 01 CIF_DD5
+GPIO_49 0 O 00
+GPIO_50 1 I 01 CIF_DD3
+GPIO_51 1 I 01 CIF_DD2
+GPIO_52 1 I 01 CIF_DD4
+GPIO_53 0 O 02 CIF_MCLK
+GPIO_54 1 I 03 CIF_PCLK
+GPIO_55 0 I 01 CIF_DD1
+GPIO_56 1 O 00
+GPIO_57 0 O 00
+GPIO_58 1 O 02 LDD0
+GPIO_59 1 O 02 LDD1
+GPIO_60 1 O 02 LDD2
+GPIO_61 1 O 02 LDD3
+GPIO_62 1 O 02 LDD4
+GPIO_63 1 O 02 LDD5
+GPIO_64 1 O 02 LDD6
+GPIO_65 1 O 02 LDD7
+GPIO_66 1 O 02 LDD8
+GPIO_67 1 O 02 LDD9
+GPIO_68 1 O 02 LDD10
+GPIO_69 1 O 02 LDD11
+GPIO_70 1 O 02 LDD12
+GPIO_71 1 O 02 LDD13
+GPIO_72 1 O 02 LDD14
+GPIO_73 1 O 02 LDD15
+GPIO_74 1 O 02 L_LCLK_RD
+GPIO_75 1 O 02 L_LCLK_A0
+GPIO_76 1 O 02 L_PCLK_WR
+GPIO_77 1 O 02 L_BIAS
+GPIO_78 0 O 00
+GPIO_79 0 O 00
+GPIO_80 1 I 00
+GPIO_81 1 I 02 CIF_DD0
+GPIO_82 0 O 00
+GPIO_83 0 O 00
+GPIO_84 1 I 03 CIF_FV
+GPIO_85 1 I 03 CIF_LV
+GPIO_86 1 I 00
+GPIO_87 0 I 00
+GPIO_88 0 O 00
+GPIO_89 0 O 01 AC97_SYSCLK
+GPIO_90 0 O 00
+GPIO_91 1 O 00
+GPIO_92 0 O 00
+GPIO_93 1 I 02 CIF_DD6
+GPIO_94 0 I 00
+GPIO_95 0 O 00 USB_POWER
+GPIO_96 1 O 00
+GPIO_97 0 I 03 KP_MKIN3
+GPIO_98 1 O 00
+GPIO_99 1 I 00
GPIO100 0 I 01 KP_MKIN0
GPIO101 0 I 01 KP_MKIN1
GPIO102 0 I 01 KP_MKIN2
Modified: linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/palmz72.c
===================================================================
--- linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/palmz72.c 2006-10-06 17:50:43 UTC (rev 622)
+++ linux4palm/linux/trunk/arch/arm/mach-pxa/palmz72/palmz72.c 2006-10-12 17:48:14 UTC (rev 623)
@@ -54,6 +54,9 @@
#define IR_TRANSCEIVER_OFF \
SET_HX4700_GPIO_N(IR_ON, 0)
+#define LED_ON SET_GPIO(GPIO_NR_ZIRE72_LED,1)
+#define LED_OFF SET_GPIO(GPIO_NR_ZIRE72_LED,0)
+
static int palmz72_udc_is_connected(void)
{
int ret = !(GET_GPIO(GPIO_NR_PALMZ72_USB_DETECT));
@@ -293,10 +296,12 @@
pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
+ pxa_gpio_mode(GPIO_NR_ZIRE72_LED_MD);
// testing
// GPSR(91) = GPIO_bit(91);
-
+ LED_ON;
+
switch(palmz72lcd.bpp)
{
case 8:
@@ -316,6 +321,7 @@
palmlz72_irda_set_txrx (NULL, PXA_SERIAL_TX);
#endif
#endif
+ LED_OFF;
}
MACHINE_START(PALMZ72, "Palm Zire 72")
Modified: linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmz72-gpio.h
===================================================================
--- linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmz72-gpio.h 2006-10-06 17:50:43 UTC (rev 622)
+++ linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmz72-gpio.h 2006-10-12 17:48:14 UTC (rev 623)
@@ -19,6 +19,8 @@
#define GPIO_NR_ZIRE72_KP_MKOUT1 104
#define GPIO_NR_ZIRE72_KP_MKOUT2 105
+#define GPIO_NR_ZIRE72_LED 88
+#define GPIO_NR_ZIRE72_LED_MD GPIO_NR_ZIRE72_LED
#define GPIO_NR_ZIRE72_KP_MKIN3_MD (GPIO_NR_ZIRE72_KP_MKIN3 | GPIO_ALT_FN_3_IN)
#define GPIO_NR_ZIRE72_KP_MKIN0_MD (GPIO_NR_ZIRE72_KP_MKIN0 | GPIO_ALT_FN_1_IN)
Modified: linux4palm/linux/trunk/include/asm-arm/arch-pxa/pxa-regs.h
===================================================================
--- linux4palm/linux/trunk/include/asm-arm/arch-pxa/pxa-regs.h 2006-10-06 17:50:43 UTC (rev 622)
+++ linux4palm/linux/trunk/include/asm-arm/arch-pxa/pxa-regs.h 2006-10-12 17:48:14 UTC (rev 623)
@@ -101,6 +101,7 @@
#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
#define DCSR_ENRINTR (1 << 9) /* The end of Receive */
+#define DCSR_EORINTR (1 << 9) /* The end of Receive */
#endif
#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
@@ -800,11 +801,18 @@
#define UDC_INT_PACKETCMP (0x1)
#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+/* Older defines, do not use. */
#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
+/* New defines. */
+#define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */
+#define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */
+#define UDCISR1_IRRU (1 << 29) /* IntEn - Resume */
+#define UDCISR1_IRSU (1 << 28) /* IntEn - Suspend */
+#define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */
#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
@@ -1835,6 +1843,8 @@
#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
#define LCSR __REG(0x44000038) /* LCD Controller Status Register */
+#define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */
+#define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */
#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
#define TMEDCR __REG(0x44000044) /* TMED Control Register */
@@ -1844,6 +1854,10 @@
#define LCCR3_4BPP (2 << 24)
#define LCCR3_8BPP (3 << 24)
#define LCCR3_16BPP (4 << 24)
+#define LCCR3_18BPP (6 << 24)
+#define LCCR3_19BPP (8 << 24)
+#define LCCR3_24BPP (9 << 24)
+#define LCCR3_25BPP (10<< 24)
#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
@@ -2008,6 +2022,104 @@
#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
+/* Overlay1 & Overlay2 & Hardware Cursor */
+#define LCSR1_SOF1 (1 << 0)
+#define LCSR1_SOF2 (1 << 1)
+#define LCSR1_SOF3 (1 << 2)
+#define LCSR1_SOF4 (1 << 3)
+#define LCSR1_SOF5 (1 << 4)
+#define LCSR1_SOF6 (1 << 5)
+
+#define LCSR1_EOF1 (1 << 8)
+#define LCSR1_EOF2 (1 << 9)
+#define LCSR1_EOF3 (1 << 10)
+#define LCSR1_EOF4 (1 << 11)
+#define LCSR1_EOF5 (1 << 12)
+#define LCSR1_EOF6 (1 << 13)
+
+#define LCSR1_BS1 (1 << 16)
+#define LCSR1_BS2 (1 << 17)
+#define LCSR1_BS3 (1 << 18)
+#define LCSR1_BS4 (1 << 19)
+#define LCSR1_BS5 (1 << 20)
+#define LCSR1_BS6 (1 << 21)
+
+#define LCSR1_IU2 (1 << 25)
+#define LCSR1_IU3 (1 << 26)
+#define LCSR1_IU4 (1 << 27)
+#define LCSR1_IU5 (1 << 28)
+#define LCSR1_IU6 (1 << 29)
+
+#define LDCMD_SOFINT (1 << 22)
+#define LDCMD_EOFINT (1 << 21)
+
+
+#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */
+#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */
+#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */
+#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */
+#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */
+#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */
+#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */
+#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */
+
+#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */
+#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */
+#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */
+#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */
+#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */
+#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */
+
+#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */
+#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */
+#define CCR_CEN (1<<31) /* Enable bit for Cursor */
+
+/* LCD registers */
+#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */
+#define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */
+#define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
+#define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
+#define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */
+#define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */
+#define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */
+#define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */
+#define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */
+#define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */
+#define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */
+#define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */
+#define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */
+#define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */
+#define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */
+#define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */
+#define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */
+#define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */
+#define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */
+#define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */
+#define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */
+#define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */
+#define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */
+
+#define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */
+#define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */
+#define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */
+#define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */
+#define CCR __REG(0x44000090) /* Cursor Control Register */
+
+#define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */
+#define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */
+
/*
* Memory controller
*/
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
