GXemul Code2

Status: Alpha

Brought to you by: gavare

Commit [r6498] Maximize Restore History

Implementing the first RISC-V instruction: c.addi

Authored by: debug 2021-04-10

Browse code at this revision

Parent: [r6497]

Child: [r6499]

changed	/gxemul/trunk/doc/TODO.html
changed	/gxemul/trunk/src/core/debugmsg.c
changed	/gxemul/trunk/src/cpus/cpu_dyntrans.c
changed	/gxemul/trunk/src/cpus/cpu_riscv.c
changed	/gxemul/trunk/src/cpus/cpu_riscv_instr.c
changed	/gxemul/trunk/src/include/cpu_riscv.h

/gxemul/trunk/doc/TODO.html Diff Switch to side-by-side view

/gxemul/trunk/src/core/debugmsg.c Diff Switch to side-by-side view

/gxemul/trunk/src/cpus/cpu_dyntrans.c Diff Switch to side-by-side view

/gxemul/trunk/src/cpus/cpu_riscv.c Diff Switch to side-by-side view

/gxemul/trunk/src/cpus/cpu_riscv_instr.c Diff Switch to side-by-side view

/gxemul/trunk/src/include/cpu_riscv.h Diff Switch to side-by-side view