GXemul Code2

Expanding the MIPS lw/sw 2-, 3-, and 4-instruction combinations (when loading/storing using the same base register) so that they are used also when emulating 64-bit CPUs such as the R4400. (Note: still lw/sw, i.e. 32-bit loads and stores, NOT ld/sd.) Also stretching it to 5-instruction-sequences.

Updating the TODO.

Adding a minimal section on Address Translation.

Removing more testmips stuff from the new framework.

Do not include "make test" when doing a make install; make test is only for the new framework anyway.

Minor update.

Getting rid of the "unstable" component/machine concept.

Fix warning.

Include testmachines in index.

Moving testmachine stuff into a separate section.