GXemul Code2

Include missing iomanip header.

Applying a patch from Andreas Gustafsson (gson) to set the SA_RESTART flag in the timer sigaction call.

More work on RISC-V: the first instruction (JAL / J) can be disassembled.

Adding a skeleton RISC-V CPU and RISC-V "virt" machine. Refactoring some parts of the new framework to deal better with variable length instructions during disassembly.

Use bold font rather than brackets around debug messages, when running from a terminal.

Implementing the ARM sbfx instruction.

Implementing the ARM rev, uxtab, and uxtah instructions.

Almost beginning on Device Tree stuff for ARM Android machines.

Implementing the ARM mls instruction.

It seems that Linux/Android wants 0xffffffff as the architecture ID for some machines.