GXemul Code2

Status: Alpha

Brought to you by: gavare

Code2 Commit Log

Commit	Date
[r6150] by debug Implementing ARM ldrex/strex (load-linked / store-conditional).	2019-02-06 07:56:55	Tree
[r6149] by debug Beginning on a hack to allow emulated SGI O2 machines have more than 256 MB of RAM. Works with OpenBSD/sgi so far.	2019-02-06 06:52:32	Tree
[r6148] by debug Skip the cast align warnings for now. Perhaps there is time in the future to revisit this.	2019-02-05 05:38:59	Tree
[r6147] by debug Fix minor warnings.	2019-01-27 13:32:30	Tree
[r6146] by debug Fix size_t vs int warning.	2019-01-27 13:30:07	Tree
[r6145] by debug Fixing potential compiler warning/error.	2019-01-27 13:24:51	Tree
[r6144] by debug Disassembly of the "mls" ARM instruction, and minor debug updates.	2019-01-20 08:59:12	Tree
[r6143] by debug Some more debug register values, just in case.	2019-01-20 08:58:52	Tree
[r6142] by debug Copyright.	2019-01-20 08:58:33	Tree
[r6141] by debug Making sure that when writing to mirrored RAM, any dyntrans translations made in either the mirror or mirrored ranges are invalidated.	2019-01-20 08:57:39	Tree

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