GXemul Code2

Implementing happy case of an "lda" i960 instruction which has an extra displacement word, i.e. non-standard dyntrans instruction length.

Beginning to implement i960 dyntrans instructions.

Updating documentation comments.

Implementing the rest of i960CA REG instruction disasm.

Beginning to add some REG instruction disassembly. Also correcting the order of the arguments for Store MEM instructions.

Basic b.out file loader.

Implementing COBR disassembly.

i960 MEM instruction disassembly has now been implemented.

Adding more i960 registers as state variables.

Comment about RAM amounts.