GXemul Code2

Reimplementing the M88k cmp and cmp_imm instructions.

Reimplementing the M88K br, or, and or.u instructions.

Continuing on write handlers for variables (root.step),
beginning on component tree snapshotting (using Clone). The
backward-step command now works reasonably well (but the only
snapshot taken so far is at step=0).

M88K model can now also be set.

Most likely, iirc, RAM begins at offset 0 in the O2.

MIPS zr register is now read-only, the MIPS "model" variable can be changed (and m_type is internally updated correctly).

Beginning on variable write handlers.

Merging in HISTORY file entries from the C++ branch into the main HISTORY file, for preservation.

Partial support for choosing MIPS ABI (affects disassembly and register dumps, mostly).

Separating out the dyntrans specific parts of CPUComponent into another base class, CPUDyntransComponent, so that it in theory is possible to implement non-dyntrans CPUs.