GXemul Code2

Continuing on the dyntrans core loop (inlined instruction calls first, then run a few remaining calls).

Continuing on the dyntrans core loop; single-step, starting in delay slot, fault in delay slot, etc.

Beginning on implementing branches: the MIPS "b" instruction, with delay slot (both continuous execution, and single-stepping with pause in the middle of the branch, etc).

Nicer spacing between steps when running multiple steps.

Two MIPS16 instructions can be disassembled; disassembly address is now not necessarily the same as m_pc (e.g. on MIPS16, the lowest bit is cleared).

Longer help message (with example) for the "add" command.

Two MIPS16 instructions can be disassembled; disassembly address is now not necessarily the same as m_pc (e.g. on MIPS16, the lowest bit is cleared).

Removing unnecessary X11 includes during the build, and making sure that all tests pass even in 'stable' builds.

Adding a 'raw' file loader, and a dummy SGI IP32 template.

Arguments can now be passed during component creation, e.g. nr CPUs, CPU model, or ram amount for a template machine. (But CPU model is ignored by the CPUs, because there are no write handlers for variables yet...)