GXemul Code2
Status: Alpha
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Code2 Commit Log
| Commit | Date | |
|---|---|---|
| 2006-09-30 05:57:08 | Tree | |
|
[r4454]
by
debug
Adding disassembly support for more MIPS64 revision 2 opcodes (seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu, dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also implementing seb, seh, dsbh, dshd, and wsbh. |
2006-09-30 05:39:44 | Tree |
|
[r4453]
by
debug
The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c, causing TLB lookups to sometimes succeed when they should have failed. (A big thank you to Juli Mallett for noticing the problem.) |
2006-09-30 03:19:18 | Tree |
| 2006-09-29 10:29:12 | Tree | |
|
[r4451]
by
debug
Re-implementing checks for coprocessor availability for MIPS cop0 instructions. (Thanks to Carl van Schaik for noticing the lack of cop0 availability checks.) Implementing an instruction combination hack which treats NetBSD/pmax idle loop as a wait-like instruction. |
2006-09-29 10:17:50 | Tree |
| 2006-09-29 10:16:26 | Tree | |
| 2006-09-26 08:49:35 | Tree | |
| 2006-09-26 08:49:18 | Tree | |
|
[r4447]
by
debug
Adding disassembly support for some MIPS64 revision 2 instructions: ext, dext, dextm, dextu. The timer framework now works also when the MIPS wait instruction is used. |
2006-09-26 08:49:03 | Tree |
| 2006-09-23 04:41:42 | Tree |
