GXemul Code2
Status: Alpha
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Code2 Commit Log
| Commit | Date | |
|---|---|---|
|
[r4451]
by
debug
Re-implementing checks for coprocessor availability for MIPS cop0 instructions. (Thanks to Carl van Schaik for noticing the lack of cop0 availability checks.) Implementing an instruction combination hack which treats NetBSD/pmax idle loop as a wait-like instruction. |
2006-09-29 10:17:50 | Tree |
| 2006-09-29 10:16:26 | Tree | |
| 2006-09-26 08:49:35 | Tree | |
| 2006-09-26 08:49:18 | Tree | |
|
[r4447]
by
debug
Adding disassembly support for some MIPS64 revision 2 instructions: ext, dext, dextm, dextu. The timer framework now works also when the MIPS wait instruction is used. |
2006-09-26 08:49:03 | Tree |
| 2006-09-23 04:41:42 | Tree | |
|
[r4445]
by
debug
Running with -N now prints "idling" instead of bogus nr of instrs/second (which is not valid anyway) while idling. |
2006-09-23 04:10:23 | Tree |
| 2006-09-23 04:09:57 | Tree | |
|
[r4443]
by
debug
Temporarily hardcoding MIPS timer interrupt to 100 Hz. With "wait" support disabled, NetBSD/malta and Linux/malta run at correct speed. Also: Connecting dev_gt to the timer framework, so that NetBSD/cobalt runs at correct speed. |
2006-09-23 03:52:10 | Tree |
| 2006-09-23 03:51:06 | Tree |
