GXemul Code2
Status: Alpha
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Code2 Commit Log
| Commit | Date | |
|---|---|---|
| 2006-09-01 15:20:32 | Tree | |
|
[r4394]
by
debug
The VR41xx RTC now returns correct time. Connecting the VR41xx timer to the timer framework (fixed at 128 Hz, for now). |
2006-09-01 15:19:49 | Tree |
|
[r4393]
by
debug
The MIPS suspend instruction now exits the emulator, instead of being treated as a wait instruction (this causes NetBSD/hpcmips to get correct halt behavior). |
2006-09-01 15:19:01 | Tree |
|
[r4392]
by
debug
Adding a hack for MIPS [d]mfc0 select 0 (except the count register), so that the coproc register is simply copied. |
2006-09-01 13:02:54 | Tree |
| 2006-09-01 11:39:50 | Tree | |
| 2006-09-01 05:36:38 | Tree | |
| 2006-08-31 13:07:06 | Tree | |
|
[r4388]
by
debug
Fixing dev_wdc so it calculates correct (64-bit) offsets before giving them to diskimage_access(). |
2006-08-30 17:14:25 | Tree |
|
[r4387]
by
debug
The MIPS R41xx standby, suspend, and hibernate instructions now behave like the RM52xx/MIPS32/MIPS64 wait instruction. |
2006-08-30 16:16:14 | Tree |
| 2006-08-30 16:10:02 | Tree |
