From: Scott E. <sc...@ju...> - 2011-11-21 14:36:38
|
The constants you pass to CP() are defined in include/asm/arch/mux.h They refer to the MODE 0 pad function. For your example (from mux.h) ... #define CONTROL_PADCONF_GPMC_A3 0x007E #define CONTROL_PADCONF_GPMC_A4 0x0080 #define CONTROL_PADCONF_GPMC_A5 0x0082 #define CONTROL_PADCONF_GPMC_A6 0x0084 ... You want GPMC_A5 as the arg to CP() to configure that pad for GPIO_38. The 32-bit mux registers can be accessed at 16 bit offsets so it all works. On Mon, 2011-11-21 at 08:26 -0500, cod...@gm... wrote: > Hello, > > It's been a while since I've attempted to change the pin mux > configuration of GPIOs on the Gumstix Overo board. I am currently > attempting to patch overo.h with a few GPIO configurations. This file > has lines similar to "MUX_VAL(CP(<name>), (IEN | PTU | EN | M4)" > where <name> is one of the register names from the OMAP35x TRM Table > 7-4 without the "CONTROL_PADCONF_" part. > > I notice each of these PADCONF register entries in the table has > duplicates for each register, since each register is used for two > separate pads, or GPIOs. I wanted to enable GPIO 38, which would be > GPMC_A4. However GPMC_A4 is also GPIO 37 according to the table. How > do I specify which GPIO I'm trying to reference? > > Which GPIO will get enabled with MUX_VAL(CP(GPMC_A4), ( IEN | PTU > | EN | M4)? If it's GPIO 37 how do I specify GPIO 38? > > Thank you for your time, > > Wayne > ------------------------------------------------------------------------------ > All the data continuously generated in your IT infrastructure > contains a definitive record of customers, application performance, > security threats, fraudulent activity, and more. Splunk takes this > data and makes sense of it. IT sense. And common sense. > http://p.sf.net/sfu/splunk-novd2d > _______________________________________________ gumstix-users mailing list gum...@li... https://lists.sourceforge.net/lists/listinfo/gumstix-users |