Ah! It would appear you are probably correct. I was going to send a follow up inquiring how omap_mux was reporting correct the correct configuration on the pins if the register wasn't set properly, but you've cleared that up it seems. Guess I was off a row reading from the TRM.


On Jun 30, 2014 5:43 PM, "Trev Sheerin" <trev@digitalclacks.com> wrote:
I was looking at the pinmuxing using devmem2 for I2C3. SCL is configured as 0x11C which seems surprising considering the bus works just fine. What am I missing here?

Related, my project requires 3 chips on SPI1. I'm looking at remuxing CS2 for this, according to devmem2 the pin is muxed as 0x114, though all the documentation seems to indicate that this pin is for Eth0 IRQ by default. Is this a similar story to I2C3SCL?

Trev Sheerin