The DSP speed can be set via registers:
http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/p/62658/225772.aspx#225772

I don't have a simple answer yet, but the pointed me to:
spruf98h.pdf - Processor Clock Control - page 414 - section 4.12.6.1.4

I think the more useful info starts here: 
page 429 - Table 4-98 - CM_CLKSEL1_PLL_IVA2

Also on page 352:
Before any transition to OPP1 or OPP2, set the DPLL2 bypass clock to CORE_CLK/4 in the CM_CLKSEL1_PLL_IVA2[20:19] IVA2_CLK_SRC bit field. During relock phase, the DSP clock is 83 MHz. This has no effect on performance because DPLL2 relock time is only a few μs.

If I get around to figuring out how to actually set it in normal people terms I'll post again. 

AJ ONeal

On Sun, Aug 29, 2010 at 3:26 PM, J. L. <vwyodapink@gmail.com> wrote:
So is that speed (DSP) not settable then? Just curious, I am trying to
write down as much info as I can so when I get to needing that I have
the info jotted down.



On Sat, Aug 28, 2010 at 3:33 PM, AJ ONeal <coolaj86@gmail.com> wrote:
> What about the DSP? How can that speed be set?
> Thanks
> AJ ONeal
>
>
> On Fri, Aug 27, 2010 at 2:52 PM, Søren Steen Christensen
> <lists@ssc-solutions.dk> wrote:
>>
>> Just add "mpurate=720" to your bootargs variable...
>>
>> Alternatively you can use the cpufreq tools in Linux
>>  Søren
>>
>> ---
>> SSC Solutions ApS - Denmark - www.ssc-solutions.dk
>>
>>
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