I am trying to setup the LCD controller using the commands listed in the display wiki page but when I entered the pxaregs LCCR, most of the values are set to zero. I have added the console messages.


*** Welcome to Gumstix ***

U-Boot code: A3F00000 -> A3F25D1C  BSS: -> A3F5AE38

RAM Configuration:

Bank #0: a0000000 64 MB

Flash: 16 MB


Can't overwrite "serial#"

Net:   SMC91C1111-0

Hit any key to stop autoboot:  2  0



GUM> setenv bootargs console  =ttyS0,115200n8 root=1f01 rootfstype=jffs2 video=pxafb:mode:640x480-16,passive,color,hsynclen:3,right:5,left:7,vsynclen:39,pixclock:26000,hsync:1,vsync:1,pixclockpol:1

GUM> saveenv

Saving Environment to Flash...


Un-Protected 1 sectors

Erasing Flash...

. done

Erased 1 sectors

Writing to Flash... done


Protected 1 sectors

GUM> boot

Instruction Cache is ON

### JFFS2 loading 'boot/uImage' to 0xa2000000

Scanning JFFS2 FS:   | .  / - \ | .  / .  - \ | / .  - \ | .  / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / -  done.

### JFFS2 load complete: 763176 bytes loaded to 0xa2000000

## Booting image at a2000000 ...

   Image Name:   uImage

   Image Type:   ARM Linux Kernel Image (uncompressed)

   Data Size:    763112 Bytes = 745.2 kB

   Load Address: a0008000

   Entry Point:  a0008000


Starting kernel ...

Linux version 2.6.18gum (root@localhost) (gcc version 3.4.5) #1 Mon Nov 6 16:02:02 NZDT 2006
CPU: XScale-PXA255 [69052d06] revision 6 (ARMv5TE), cr=0000397f
Machine: The Gumstix Platform
Memory policy: ECC disabled, Data cache writeback
Memory clock: 99.53MHz (*27)
Run Mode clock: 398.13MHz (*4)
Turbo Mode clock: 398.13MHz (*1.0, inactive)
CPU0: D VIVT undefined 5 cache
CPU0: I cache: 32768 bytes, associativity 32, 32 byte lines, 32 sets
CPU0: D cache: 32768 bytes, associativity 32, 32 byte lines, 32 sets
Built 1 zonelists.  Total pages: 16384
Kernel command line: console=ttyS0,115200n8 root=1f01 rootfstype=jffs2 video=pxafb:mode:640x480-16,passive,color,hsynclen:3,right:5,left:7,vsynclen:39,pixclock:26000,hsync:1,vsync:1,pixclockpol:1
PID hash table entries: 512 (order: 9, 2048 bytes)
start_kernel(): bug: interrupts were enabled early
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 64MB = 64MB total
Memory: 63360KB available (1248K code, 250K data, 60K init)
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
NET: Registered protocol family 16
NET: Registered protocol family 2
IP route cache hash table entries: 512 (order: -1, 2048 bytes)
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
TCP: Hash tables configured (established 2048 bind 1024)
TCP reno registered
JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.
Initializing Cryptographic API
io scheduler noop registered (default)
pxa2xx-uart.0: ttyS0 at MMIO 0x40100000 (irq = 15) is a FFUART
pxa2xx-uart.1: ttyS1 at MMIO 0x40200000 (irq = 14) is a BTUART
pxa2xx-uart.2: ttyS2 at MMIO 0x40700000 (irq = 13) is a STUART
pxa2xx-uart.3: ttyS3 at MMIO 0x41600000 (irq = 0) is a HWUART
Probing Gumstix Flash ROM at physical address 0x00000000 (16-bit bankwidth)
Gumstix Flash ROM: Found 1 x16 devices at 0x0 in 16-bit bank
 Intel/Sharp Extended Query Table at 0x0031
Using buffer write method
cfi_cmdset_0001: Erase suspend on write enabled
Using static partitions on Gumstix Flash ROM
Creating 2 MTD partitions on "Gumstix Flash ROM":
0x00000000-0x00040000 : "Bootloader"
0x00040000-0x01000000 : "RootFS"
TCP bic registered
VFS: Mounted root (jffs2 filesystem).
Freeing init memory: 60K
NET: Registered protocol family 1
smc91x: not found (-19).
CPLD responded with: ff
Initializing random number generator... done.
Starting 32kHz clock...Settled
Set (AF1,out,clear) via /proc/gpio/GPIO12
Starting Bluetooth subsystem:Trying baud rate 57600...
Set (GPIO,out,clear) via /proc/gpio/GPIO7
Set (GPIO,out,set) via /proc/gpio/GPIO7
No response after reset
No response from BT module
Trying baud rate 921600...
Set (GPIO,out,clear) via /proc/gpio/GPIO7
Set (GPIO,out,set) via /proc/gpio/GPIO7
No response after reset
No response from BT module
Trying baud rate 115200...
Set (GPIO,out,clear) via /proc/gpio/GPIO7
Set (GPIO,out,set) via /proc/gpio/GPIO7
No response after reset
No response from BT module
Trying baud rate 57600...
Set (GPIO,out,clear) via /proc/gpio/GPIO7
Set (GPIO,out,set) via /proc/gpio/GPIO7
No response after reset
No response from BT module
Can't initialize device: Success
Starting network...
udhcpc (v0.9.9-pre) started
Dec 31 16:02:43 udhcpc[215]: udhcpc (v0.9.9-pre) started

pxa2xx_udc: version 4-May-2005
usb0: Ethernet Gadget, version: May Day 2005
usb0: using pxa2xx_udc, OUT ep2out-bulk IN ep1in-bulk STATUS ep6in-bulk
usb0: MAC 72:e2:7c:cc:a3:e1
usb0: HOST MAC 72:e2:7c:cc:a3:e2
usb0: RNDIS ready
Nothing to flush.
NET: Registered protocol family 17
udhcpc (v0.9.9-pre) started
Dec 31 16:02:44 udhcpc[247]: udhcpc (v0.9.9-pre ) started

Dec 31 16:02:44 udhcpc[247]: [truncated] m

cfio: module license 'unspecified' taints kernel.
cfio: Unknown symbol kmalloc
Dec 31 16:02:44 modprobe: FATAL: Error inserting cfio (/lib/modules/2.6.18gum/kernel/drivers/pcmcia/cfio.ko): Unknown symbol in module, or unknown parameter (see dmesg)

Dec 31 16:02:44 modprobe: FATAL: Error running install command for cfio

Error for wireless request "Set ESSID" (8B1A) :
    SET failed on device mwlan0 ; No such device.
Starting Rendezvous:
Starting dropbear sshd: OK
Starting httpd...

Welcome to the Gumstix Linux Distribution!

gumstix login: root
Welcome to Gumstix!
By default, this gumstix is configured for CF support.
Unfortunately, this means MMC support has been
disabled out of the box.  To turn on MMC and turn off CF,
edit the file /etc/modules and comment out or delete the pcmcia (CF)
line, and uncomment the MMC lines.  You then also need to comment out
or remove the line "auto mwlan0" in /etc/network/interfaces if it
exists, since it will otherwise cause the pcmcia driver to be loaded.
# pxae rre  egs LCCR

LCD Controller Control Register 0 (7-23)
LCCR0                    0x00000000  00000000 00000000 00000000 00000000
LCCR0_ENB                         0  LCD controller enable
LCCR0_CMS                         0  LCD monochrome operation enable
LCCR0_SDS                         0  LCD dual panel display enable
LCCR0_LDM                         0  LCD disable done IRQ disable
LCCR0_SFM                         0  LCD start of frame IRQ disable
LCCR0_IUM                         0  LCD fifo underrun error IRQ disable
LCCR0_EFM                         0  LCD end of frame IRQ disable
LCCR0_PAS                         0  LCD active display enable
LCCR0_DPD                         0  LCD send 8 pixel on L_DD[7:0] at each clock
LCCR0_DIS                         0  LCD controller disable
LCCR0_QDM                         0  LCD quick disable IRQ disable
LCCR0_PDD                         0  LCD palette DMA request delay
LCCR0_BM                          0  LCD branch start IRQ disable
LCCR0_OUM                         0  LCD fifo underrun IRQ disable

LCD Controller Control Register 1 (7-26)
LCCR1                    0x00000000  00000000 00000000 00000000 00000000
LCCR1_PPL                         0  LCD pixels per line (+1)
LCCR1_HSW                         0  LCD horizontal sync pulse width (+1)
LCCR1_ELW                         0  LCD end of line pixel clock wait count (+1)
LCCR1_BLW                         0  LCD beginning of line pixel clock wait count (+1)

LCD Controller Control Register 2 (7-28)
LCCR2                    0x00000000  00000000 00000000 00000000 00000000
LCCR2_LPP                         0  LCD lines per panel (+1)
LCCR2_VSW                         0  LCD vertical sync pulse width (+1)
LCCR2_EFW                         0  LCD end of frame line clock wait count (+1)
LCCR2_BFW                         0  LCD beginning of frame line clock wait count (+1)

LCD Controller Control Register 3 (7-31)
LCCR3                    0x00000000  00000000 00000000 00000000 00000000
LCCR3_PCD                         0  LCD pixel clock divisor (+1)
LCCR3_ACB                         0  LCD AC bias pin frequency (+1)
LCCR3_API                         0  LCD AC bias pin transitions per interrupt
LCCR3_VSP                         0  LCD L_FCLK vertical sync polarity active low
LCCR3_HSP                         0  LCD L_LCLK horizontal sync polarity active low
LCCR3_PCP                         0  LCD data sampled on falling edge of L_PCLK
LCCR3_OEP                         0  LCD L_BIAS output enable active low
LCCR3_BPP                         1  LCD bits per pixel
LCCR3_DPC                         0  LCD double pixel clock rate at L_PCLK