Does the CMX981 pulse its output CLK and FS during the receive cycle, or does it only pulse them during transmit and then silently wait for a reply?  From your message it sounds like it's always running the clock, but only pulses the FS on transmit and it's up to the Overo to pulse its own FS when it replies.

You might be able to use a GPIO to act as an FS, however I don't know if you'd be able to do it within that 10-12 clock cycle window.  What speed is the CMX981's clock running?

This page has some info about controlling a GPIO from the kernel:


On 8/23/2013 4:15 AM, Thomas Frank wrote:
Thank you all for providing so much information.

On 22.08.2013 23:29, Adam Reynolds wrote:
> The OMAP chips on OVERO have 5 McBSPs, but only two of them are
> available on the 70-pins (3 and 5), both of which are 4 pin McBSPs (DR,
> DX, and a common CLK and FS).  It sounds like you might need a 6-pin
> McBSP, unless you can configure the CMX981 to synchronize the input and
> output clock and FS?  Something to look into.  See more in the above
> linked TRM, chapter 21.
> -Adam

For transmitting and receiving, I have to use the clock supplied by the CMX981 and feed it to the input clock for all McBSPs (mcbsp_clks). Since there is no receiving frame sync signal (from the overo perspective) on McBSP{2,3,4,5}, do you think I could use another (non-mcbsp) signal for this purpose? I have to detect the falling edge of the frame sync to know when the word began on the receiving data stream. Additionally, I probably have to adhere to the distance between receiving and transmitting data words of 10 to 12 clock cycles. It seems like there is no setting for the CMX981 changing that.

Best Regards,

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