But the ADC clock runs at the clock speed of the system? Thats the one thing I don't understand. Maybe purely on a theoretical level, but all of these clocks are essentially the system clock but capmentalized, so they should run at the same speed, given no prescaling...
On 6/13/06, Dave Hylands <email@example.com> wrote:
> I mean on the ATMEGA128. I was reading the refference doc for the microchip
> and read that i had to set multipliers that are related to the clock to run
> the clock speed down to between 50-200 khtz. (This is all in relation to
> using the analog input on the robostix). Anyways, if you could give me a
> quick rundown of how to figure out the speed of the item called "clkADC" I
> would be very happy :)
Basically, each tick of the clock collects one more bit on an ADC
value. There's a bit of setup as well, so it actually takes 13 cycles
to collect a sample.
So it depends on how frequently you need to get a new ADC sample and
how precise it needs to be. My general rule of thumb is to pick the
lowest prescalar that gets the rate down to 200 kHz (the faster the
clkADC, the more samples/second you can make).
16000000 / 200000 = 80. So I pick the divide by 128 prescalar, which
yields 125 kHz clock rate for the ADC, which is 9615 samples/second.
Running with a slower system clock, you'd pick a different prescalar.
Vancouver, BC, Canada
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