From: Kevin K. <kev...@ch...> - 2005-03-28 17:19:07
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> It's the 2nd option: gencpu.c uses this: > printf ("return %d;\n", insn_n_cycles / 2); > So, the insns return half of the cycle counts (which is OK because the cycle > counts are all even). I'll add a *2 in m68k.c to account for this. Done. > On the other hand, this one: > > One thing is sure, it's that instructions taking a variable number of > cycles > > (MULU, MULS, DIVU, DIVS, MOVEM, condition code dependent instructions) > > aren't accounted for properly. > is a bigger problem, and I looked at the current UAE 0.8.23, it's not fixed > there either. There are unfortunately other serious errors. :-( For example, clr.l %dn is counted as taking 4 cycles. It actually takes 6 cycles. This probably affects all the instructions of the same class, i.e.: .b.w/.l #,dn #,an #,mem clr 4/6 4/6 8/12 single operand nbcd 6 6 8 instructions neg 4/6 4/6 8/12 negx 4/6 4/6 8/12 not 4/6 4/6 8/12 Kevin Kofler |