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[Greensocs-devel] Call for Papers - 8th International Symposium on Quality Electronic Design - ISQED07
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From: <cf...@is...> - 2006-07-03 22:47:20
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<title>CALL FOR PAPERS ISQED 2007 8th International Symposium=
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<p align=3D"center"><font face=3D"Trebuchet MS"><b><font color=3D"#=
800000">=0D
<font size=3D"4">CALL =0D
FOR PAPERS</font><br>=0D
<br>=0D
</font>ISQED 2007<font size=3D"2"><br>=0D
<br>=0D
</font><font color=3D"#000080">8th International Symposium & Ex=
hibits on<font size=3D"2"><br>=0D
<br>=0D
</font><font size=3D"4"><a href=3D"http://www.isqed.org/">=0D
<font color=3D"#000080">QUALITY ELECTRONIC DESIGN</font></a><br>=0D=
</font><font size=3D"2"><br>=0D
</font></font><font size=3D"2">March 26-28, 2007. San Jose, C=
A, USA<br>=0D
<br>=0D
</font></b><a eudora=3D"autourl" href=3D"http://www.isqed.org/"><b>=
<i>=0D
<font color=3D"#000080">www.isqed.org</font></i></b></a></font></p>=
=0D
<div align=3D"center">=0D
<center>=0D
<table border=3D"4" cellpadding=3D"4" style=3D"border-collapse: c=
ollapse" width=3D"50%" cellspacing=3D"0" bgcolor=3D"#FF9933">=0D
<tr>=0D
<td width=3D"100%"><font color=3D"#000080" size=3D"2" face=3D=
"Trebuchet MS">=0D
<b>Paper Submission Deadline: September 30, 2006<br>=0D=
Acceptance Notifications: November 23, 2006<br>=0D
Final Camera-Ready paper: January 3, 2007</b></font></t=
d>=0D
</tr>=0D
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</center>=0D
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<hr>=0D
<p align=3D"left"><font face=3D"Trebuchet MS"><font size=3D"2">ISQE=
D is the =0D
pioneer and leading international conference dealing with the desig=
n for =0D
manufacturability and quality issues front-to-back. ISQED spa=
ns three =0D
days, Monday through Wednesday, in three parallel tracks, hosting n=
ear 100 =0D
technical presentations, six keynote speakers, two-three panel =0D
discussions, workshops /tutorials and other informal meetings. Conf=
erence =0D
proceedings are published by IEEE Computer Society and hosted in th=
e =0D
digital library. Proceedings CD ROMs are published by ACM. In=
addition, =0D
continuing the tradition of reaching a wider readership in the IC d=
esign =0D
community, ISQED will continue to publish special issues in leading=
=0D
journals. The authors of high quality papers will be invited to sub=
mit an =0D
extended version of their papers for the special journal issues. <b=
r>=0D
<br>=0D
</font><font color=3D"#800000"><b><font size=3D"2">Papers are reque=
sted in the =0D
following areas:<br>=0D
<br>=0D
</font></b></font><font size=3D"2">A pioneer and leading multidisci=
plinary =0D
conference, ISQED accepts and promotes papers related to the =0D
manufacturing, VLSI design and EDA. Authors are invited to submit p=
apers =0D
in the various disciplines of high level design, circuit design, te=
st & =0D
verification, design automation tools; processes; flows, device mod=
eling, =0D
semiconductor technology, and advance packaging. <br>=0D
<br>=0D
</font><b><font size=3D"2" color=3D"#000080">1. Manufacturing, proc=
ess, =0D
devices<br>=0D
</font><font size=3D"2">=0D
<x-tab> </x-tab></fo=
nt></b><font size=3D"2">1.1 Design for =0D
Manufacturability & Quality (DFMQ)<br>=0D
<x-tab> </x-tab>1.2 =
Effects of Technology on IC Design, =0D
Performance, Reliability, and Yield (TRD)<br>=0D
<br>=0D
</font><b><font size=3D"2" color=3D"#000080">2. Design<br>=0D
</font><font size=3D"2">=0D
<x-tab> </x-tab></fo=
nt></b><font size=3D"2">2.1 System-level Design, =0D
Methodologies & Tools (SDM)<br>=0D
<x-tab> </x-tab>2.2 =
Package - Design Interactions & Co-Design (PDI)<br>=0D
<x-tab> </x-tab>2.3 =
Robust Device, Interconnect, and Circuits (RDIC)<br>=0D
<br>=0D
</font><b><font size=3D"2" color=3D"#000080">3. EDA/CAD<br>=0D
</font><font size=3D"2">=0D
<x-tab> </x-tab></fo=
nt></b><font size=3D"2">3.1 EDA Methodologies, =0D
Tools, & IP Cores; Interoperability and Reuse(EDA)<br>=0D=
<x-tab> </x-tab>3.2 =
Design Verification and Design for Testability =0D
(DVFT) <br>=0D
<x-tab> </x-tab>3.3 =
Physical Design, Methodologies & Tools (PDM)<br>=0D
<br>=0D
The details of various topics of paper submission is as follows:<br=
>=0D
<br>=0D
</font><font color=3D"#000080"><b><font size=3D"2">Design for =0D
Manufacturability & Quality (DFMQ)<br>=0D
</font></b></font><font size=3D"2">Analysis, modeling, and abstract=
ion of =0D
manufacturing process parameters and effects for highly predictable=
=0D
silicon performance. Design and synthesis of high complexity =
ICs: signal =0D
integrity, transmission line effects, OPC, phase shifting,&nb=
sp; and =0D
sub-wavelength lithography, manufacturing yield and technology =0D
capability. Design for diagnosability, defect detection=
and tolerance; =0D
self-diagnosis, calibration and repair. Design and manufactur=
abilty =0D
issues for Digital, analog, mixed signal, RF, MEMS, opto-electronic=
, =0D
biochemical-electronic, and nanotechnology based ICs. Redundency an=
d other =0D
yield improving techniques. Design quality definitions and standard=
s; =0D
design quality metrics to track and assess the quality of electroni=
c =0D
circuit design, as well as the quality of the design process itself=
; =0D
design quality assurance techniques. Global, social, and econ=
omic =0D
implications of design quality. Design metrics, methodologies=
and flows =0D
for custom, semi-custom, ASIC, FPGA, RF, memory, networking circuit=
, etc. =0D
with emphasis on quality. Design metrics and quality standard=
s for SoC, =0D
and SiP.<br>=0D
<br>=0D
<font color=3D"#000080"><b>Package - Design Interactions & Co-D=
esign (PDI)<br>=0D
</b></font>Silicon and package co-design and impact on product qual=
ity. 3D =0D
design challenges. Electrical and thermal model of package an=
d =0D
package-die interactions. SoC versus system in a package (SiP=
) =0D
tradeoffs. di/dt modeling techniques. MCM and other packaging=
techniques. =0D
Die and package power delivery modeling and simulation, heat sink =0D=
technology modeling, design and optimization. <br>=0D
<br>=0D
<font color=3D"#000080"><b>Design Verification and Design for Testa=
bility (DVFT)<br>=0D
</b></font>Hardware and Software, Formal and simulation based desig=
n =0D
verification techniques to ensure the functional correctness of har=
dware =0D
early in the design cycle. DFT and BIST for digital and SoC. =
DFT for =0D
analog/mixed-signal ICs and systems-on-chip, DFT/BIST for memories.=
Test =0D
synthesis and synthesis for testability. DFT economics, DFT c=
ase =0D
studies. DFT and ATE. Fault diagnosis, IDDQ test,=
novel test methods, =0D
effectiveness of test methods, fault models and ATPG, and DPP=
M =0D
prediction. SoC/IP testing strategies. <br>=0D
<br>=0D
<font color=3D"#000080"><b>Robust Device, Interconnect, and Circuit=
s (RDIC)<br>=0D
</b></font>Device, substrate, interconnect, circuit , and IP block =
=0D
modeling and simulation techniques; quality metrics, model or=
der =0D
reduction; CMOS, Bipolar, and SiGe HBTs device modeling in the cont=
ext of =0D
advanced digital, RF and high-speed circuits. Modeling and si=
mulation of =0D
novel device and interconnect concepts. Signal integrity analysis: =
=0D
coupling, inductive and charge sharing noise; noise avoidance techn=
iques. =0D
Power grid design, analysis and optimization; timing analysis and =0D=
optimization; thermal analysis and design techniques for thermal =0D=
management. Modeling statistical process variations to improv=
e design =0D
margin and robustness, use of statistical circuit simulators. =0D
Power-conscious design methodologies and tools; low power devices, =
=0D
circuits and systems; power-aware computing and communication; =
; =0D
system-level power optimization and management. Design techniques f=
or =0D
leakage current management. <br>=0D
<br>=0D
<font color=3D"#000080"><b>EDA Methodologies, Tools, & IP Cores=
; =0D
Interoperability and Reuse (EDA)<br>=0D
</b></font>EDA tools addressing design quality. Management of desig=
n =0D
process, design flows and design databases. EDA tools interoperabil=
ity =0D
issues and implications. Effect of emerging technologies, processes=
& =0D
devices on design flows, tools, and tool interoperability. Emerging=
EDA =0D
standards. EDA design methodologies and tools that address issues w=
hich =0D
impact the quality of the realization of designs into physical inte=
grated =0D
circuits. IP modeling and abstraction. Design and maintenance of =0D=
technology independent hard and soft IP blocks. Methods and tools f=
or =0D
analysis, comparison and qualification of libraries and hard IP blo=
cks. =0D
Challenges and solutions of the integration, testing, and qualifyin=
g of IP =0D
blocks from multiple vendors. Third party testing of IP blocks. Ris=
k =0D
management of IP reuse. IP authoring tools and methodologies.<br>=0D=
<br>=0D
<font color=3D"#000080"><b>Physical Design, Methodologies & Too=
ls (PDM)<br>=0D
</b></font>Physical synthesis flows for correct-by-construction qua=
lity =0D
silicon, implementation of large SoC designs. Tool frameworks=
and =0D
datamodels for tightly integrated incremental synthesis, placement,=
=0D
routing, timing analysis and verification. Placement, optimiz=
ation, and =0D
routing techniques for noise sensitivity reduction and fixing. =
; Algorithms =0D
and flows for harnessing crosstalk-delay during physical synthesis.=
Tool =0D
flows and techniques for antenna rule and electromigration rule avo=
idance =0D
and fixing. Spare-cell strategies for ECO, decoupling capacit=
ance and =0D
antenna rule fixing. Planning tools for predictable high-curr=
ent, =0D
low-voltage power distribution. Reliable clock tree generation and =
clock =0D
distribution methodologies for Gigahertz designs. EDA tools, =
design =0D
techniques, and methodologies, dealing with issues such as: timing =
=0D
closure, R, L, C extraction, ground/Vdd bounce, signal noise/cross-=
talk =0D
/substrate noise, voltage drop, power rail integrity, electromigrat=
ion, =0D
hot carriers, EOS/ESD, plasma induced damage and other yield limiti=
ng =0D
effects, high frequency effects, thermal effects, power estimation,=
=0D
EMI/EMC, proximity correction & phase shift methods, verificati=
on (layout, =0D
circuit, function, etc.).<br>=0D
<br>=0D
<font color=3D"#000080"><b>Effects of Technology on IC Design, Perf=
ormance, =0D
Reliability, and Yield (TRD)<br>=0D
</b></font>Effect of emerging processes & devices on design?s t=
ime to =0D
market, yield, reliability, and quality. Emerging issues in D=
SM CMOS: =0D
e.g. sub-threshold leakage, gate leakage, technology road mapping a=
nd =0D
technology extrapolation techniques. New and novel technologi=
es such as =0D
SOI, Double-Gate(DG)-MOSFET, Gate-All-Around (GAA)-MOSFET, Vertical=
-MOSFET, =0D
strained CMOS, high-bandwidth metallization, etc. Challenges =
of =0D
mixed-signal design in digital CMOS or BiCMOS technology, including=
issues =0D
of substrate coupling, cross-talk and power supply noise. Sig=
nificance of =0D
reliability effects such as gate oxide integrity, electromigr=
ation, ESD, =0D
etc., in relation to electronic design. Impacts of proc=
ess technologies =0D
on circuit design and capabilities (e.g. low-Vt transistors versus =
=0D
increased off-state leakages) and the accuracy, use and implementat=
ion of =0D
SPICE models that faithfully reflect process technologies. Successf=
ul =0D
applications of TCAD to circuit design. <br>=0D
<br>=0D
<font color=3D"#000080"><b>System-level Design, Methodologies &=
Tools (SDM)<br>=0D
</b></font>Global, Social, and Economical Implications of Electroni=
c =0D
System and Design Quality. Emerging standards and regulations influ=
encing =0D
system quality. Emerging system-level design paradigms, methods and=
tools =0D
aiming at quality. System-level design process and flow management.=
=0D
System-level design modeling, analysis and synthesis, estimation an=
d =0D
verification for correct high-quality hardware/software systems. =0D=
Responsive, secure, and defect tolerant systems. New concepts, meth=
ods and =0D
tools addressing system-level design complexity and multitude of as=
pects. =0D
Methods and tools addressing the usage of technology information an=
d =0D
manufacturing feedback in the system-, RTL- and logic level design.=
The =0D
influence of the nanometer technologies' (application-dependent) yi=
eld and =0D
other issues on the system-, RTL- and logic-level design. System-le=
vel =0D
trade-off analysis and multi-objective (yield, power, delay, area ?=
) =0D
optimization. Effective and efficient design, implementation, analy=
sis and =0D
validation of large SoCs integrating IP blocks from multiple vendor=
s.<br>=0D
<br>=0D
<br>=0D
<font color=3D"#800000"><b>Submission of Papers<br>=0D
</b></font>Paper submission must be done on-line via the conference=
web =0D
site at <a href=3D"http://www.isqed.org/" eudora=3D"autourl">www.is=
qed.org</a>. =0D
Authors should submit FULL-LENGTH, original, unpublished papers (Mi=
nimum =0D
4, maximum 6 pages) along with an abstract of about 200 words. =
; Please =0D
check the as-printed appearance of your paper before uploading. To =
permit =0D
a blind review, do not include name(s) or affiliation(s) of t=
he author(s) =0D
on the manuscript and abstract. The complete contact author i=
nformation =0D
needs to be entered separately. When ready to submit your paper hav=
e the =0D
following information ready:<br>=0D
<br>=0D
I<x-tab> </x-tab>Title of =
the paper<br>=0D
II<x-tab> </x-tab>Name, affiliat=
ion, complete mailing address and =0D
phone, fax, and email of the first author<br>=0D
III<x-tab> </x-tab>Name, affiliations,=
city, state, country of =0D
additional authors<br>=0D
IV<x-tab> </x-tab>Person to whom=
correspondence should be sent, if =0D
other than the 1st author<br>=0D
V<x-tab> </x-tab>Suggested=
area (as listed above)<br>=0D
<br>=0D
The guidelines for the final paper format are provided on the confe=
rence =0D
web site at <a href=3D"http://www.isqed.org/" eudora=3D"autourl">ww=
w.isqed.org</a>.=0D
<u>Authors of the submitted papers must register and attend the con=
ference =0D
for their paper to be published</u>. <br>=0D
<br>=0D
Please note the following important dates:</font></font></p>=0D
<table border=3D"4" cellpadding=3D"4" style=3D"border-collapse: col=
lapse" width=3D"50%" cellspacing=3D"0" bgcolor=3D"#FF9933">=0D
<tr>=0D
<td width=3D"100%"><font color=3D"#000080" size=3D"2" face=3D"T=
rebuchet MS">=0D
<b>Paper Submission Deadline: September 30, 2006<br>=0D
Acceptance Notifications: November 23, 2006<br>=0D
Final Camera-Ready paper: January 3, 2007</b></font></td>=
=0D
</tr>=0D
</table>=0D
<p align=3D"left"><font size=3D"2" face=3D"Trebuchet MS"><b>=0D
<font color=3D"#800000"><br>=0D
</font><font color=3D"#000080">About ISQED<br>=0D
</font></b>The International Symposium on Quality Electronic Design=
=0D
(ISQED), is a premier Design & Design Automation conference, ai=
med at =0D
bridging the gap between and integration of, electronic design tool=
s and =0D
processes, integrated circuit technologies, processes & manufac=
turing, to =0D
achieve design quality. ISQED is the pioneer and leading conference=
=0D
dealing with design for manufacturability and quality issues =
=0D
front-to-back. The conference provides a forum to present and excha=
nge =0D
ideas and to promote the research, development, and application of =
design =0D
techniques & methods, design processes, and EDA design methodol=
ogies and =0D
tools that address issues which impact the quality of the realizati=
on of =0D
designs into physical integrated circuits. The conference attendees=
are =0D
primarily designers of the VLSI circuits & systems (IP & So=
C), those =0D
involved in the research, development, and application of EDA/CAD T=
ools & =0D
design flows, process/device technologists, and semiconductor =0D
manufacturing specialists including equipment vendors. ISQED emphas=
izes a =0D
holistic approach toward design quality and intends to highlight an=
d =0D
accelerate cooperation among the IC Design, EDA, Semiconductor Proc=
ess =0D
Technology and Manufacturing communities.</font></p>=0D
<hr></td>=0D
</tr>=0D
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