Robert Pearce reports that the midrange PICs
(specifically the 16f628) EEPROM peripheral is not working.
I've been trying to simulate some 16F628 code, using
because 0.21.4 won't work for me, but I don't think
this has changed. Here's what we writes on the gpsim
development mailing list:
In my code I have the following function:
movf cvaddr,w ; Point to the EEPROM copy of data
bsf STATUS,RP0 ; Address the EE registers
bsf EECON1,WREN ; Enable write operations
bcf INTCON,GIE ; Disable interrupts for the
movlw 0x55 ; \ movwf EECON2 ; \ movlw 0xAA ; > This sequence triggers
movwf EECON2 ; /
bsf EECON1,WR ; /
; bsf INTCON,GIE ; Re-enable interrupts
nop ; We're not using interrupts
bcf EECON1,WREN ; Write protect again
The code then waits for the EEIF bit or a time-out.
When simulated it
always hits the time-out, and I see the message:
EEPROM::callback() bad eeprom state 3
I think, from looking at the eeprom.cc code, that what
is happening is
that when my code clears WREN after initiating a write,
GPSim is setting
the EE state to "unarmed", with the result that on
completion of the
programming time the callback fails. Indeed, if I
remove the line that
clears WREN then the EEPROM write works.
However, the data sheet (DS40300C page 89) explicitly
"After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle."
It looks like this is a bug in the EEPROM simulation,
but I don't want
to try fixing it myself (partly because I'm not
convinced I fully
understand the eestate workings, and partly because I
can't get the
latest CVS to work so I can't fix the current version).