#129 POSTDEC2 bug?



Instead of putting values in REG0x10 and REG0x09, gpsim is putting values in
REG0x00 and REG0xFFF. I am not sure if this is happening due to the recent fix
that was put in for the movff PLUSW2,POSTDEC2 issue.

this is the gpsim output:

gpsim test_postdec2_bug.cod

gpsim - the GNUPIC simulator
version: Release 0.26.99

type help for help

P18F4455 does not support USB registers and functionality

Config3H_2x21::set ( 0x83 )
**gpsim> Program_Counter16::put_value 0x0
0x0000000000000001 p18f4455 0x0000 0xEE20 lfsr 2,0x10
18:    lfsr 2,0x10
  Wrote: 0x0000 to pclath(0x0FFA) was 0x0000
  Wrote: 0x0000 to pclatu(0x0FFB) was 0x0000
  Wrote: 0x0000 to stkptr(0x0FFC) was 0x0000
  Wrote: 0x0000 to tosl(0x0FFD) was 0x0000
  Wrote: 0x0000 to tosh(0x0FFE) was 0x0000
  Wrote: 0x0000 to tosu(0x0FFF) was 0x0000
  Wrote: 0x0010 to fsrl2(0x0FD9) was 0x0000
  Wrote: 0x0000 to fsrh2(0x0FDA) was 0x0000
0x0000000000000002 p18f4455 0x0004 0x0E01 movlw 0x01
19:    movlw 0x1
  Wrote: 0x0001 to W(0x0FE8) was 0x0000
0x0000000000000004 p18f4455 0x0006 0xCFE8 movff W,postdec2
20:    movff WREG,POSTDEC2
  Read: 0x0001 from W(0x0FE8)
  Wrote: 0x0000 to postdec2(0x0FDD) was 0x0000
  Wrote: 0x00FF to fsrl2(0x0FD9) was 0x0010
  Wrote: 0x000F to fsrh2(0x0FDA) was 0x0000
  Wrote: 0x0001 to REG000(0x0000) was 0x0000
0x0000000000000005 p18f4455 0x000A 0x0E02 movlw 0x02
22:    movlw 0x2
  Wrote: 0x0002 to W(0x0FE8) was 0x0001
0x0000000000000007 p18f4455 0x000C 0xCFE8 movff W,postdec2
23:    movff WREG,POSTDEC2
  Read: 0x0002 from W(0x0FE8)
  Wrote: 0x0000 to postdec2(0x0FDD) was 0x0000
  Wrote: 0x00FE to fsrl2(0x0FD9) was 0x00FF
  Wrote: 0x000F to fsrh2(0x0FDA) was 0x000F
  Wrote: 0x0002 to tosu(0x0FFF) was 0x0000

;==== test_postdec2_bug.asm BEGIN

errorlevel 0
   list p=18f4455 ; set processor type
   list n=0 ; supress page breaks in list file
   include <p18f4455.inc>

popf macro x
   movff PREINC2,x
RESET_VECTOR CODE 00000h ; Reset and Interrupt Vectors
   pagesel start
   global start
   global start
   lfsr 2,0x10
   movlw 0x1
   movff WREG,POSTDEC2
   ; 0x10 = 0x1
   movlw 0x2
   movff WREG,POSTDEC2
   ; 0x09 = 0x2

   popf SSPBUF
   ; sspbuf must be 0x2
   movff SSPBUF,WREG
   popf SSPBUF
   ; sspbuf must be 0x1
   global endp
   goto start
;==== test_postdec2_bug.asm END



  • Robert Pearce

    Robert Pearce - 2011-06-06

    This certainly shouldn't be a result of the recent change to postdec because the code presented here won't invoke any of the bits of GPSim that I changed.

  • Robert Pearce

    Robert Pearce - 2011-06-06

    A question: what happens if you write your code a bit more realistically, such as with a goto at the reset vector and the lfsr not being the very first instruction? My answer: it works correctly. That suggests the bug should be easily fixed.

  • Robert Pearce

    Robert Pearce - 2011-06-06
    • assigned_to: nobody --> bdt-rob
  • Robert Pearce

    Robert Pearce - 2011-06-19
    • status: open --> closed-fixed
  • Robert Pearce

    Robert Pearce - 2011-06-19

    Fix committed at r2179. The mechanism for preventing double-decrements was causing FSR setting to fail on the very first clock cycle.



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