#12 undefined symbols from in VHDL object outputs during link

Rachel Mant

During runs using Xilinx's Unisim and EDK IP Cores, with their IEEE library implementation available to fill in the "missing" (non-standard) blanks specific to their code, when linking my own code, I get long lists of errors complaining about undefined references in their IEEE library as shown in the attached file.

If I use their IEEE library on it's own with Unisim then I get no such problems, but when I ask GHDL to link in anything from in their EDK IP Cores, errors from in the IEEE library ensue instead of a linked binary.

1 Attachments


  • Tristan Gingold

    Tristan Gingold - 2014-03-23


    the xilinx version of std_logic_arith is based on foreigns, so this implementation
    is xilinx specific (and not compatible with ghdl).


  • Tristan Gingold

    Tristan Gingold - 2014-03-23
    • status: open --> closed
    • assigned_to: Tristan Gingold
  • Rachel Mant

    Rachel Mant - 2014-03-23

    Hello Tristan,
    Thanks for your speedy reply.

    Your implementation of the IEEE library does not (correctly) have std_logic_arith as this is one of the non-standard additions I mentioned Xilinx has. Unfortunately it's very widely used within other code throughout their EDK IP Core library.

    I am working with a copy of the library's source from them so it is possible to replace their foreigns definitions with something from GHDL or your own IEEE library. Fortunately on checking, there are actually implementations of the functions already present within the body of the file, it's just for some reason they have the functions attributed with foreign too.

    Rachel Mant.

    Last edit: Rachel Mant 2014-03-23
  • Tristan Gingold

    Tristan Gingold - 2014-03-23

    Try to analyse with the --ieee=synopsys switch.



Log in to post a comment.

Get latest updates about Open Source Projects, Conferences and News.

Sign up for the SourceForge newsletter:

No, thanks