| 109 |
Assert statements with brackets not working for VDHL 2008 |
1.0 |
open |
|
2018-07-30
|
2018-07-31
|
|
| 106 |
Annoying warnings during initialization when "out" ports in components are not initialized in entity declaration |
1.0 |
open |
|
2016-07-26
|
2016-07-26
|
|
| 105 |
Starting and stopping dumping the signals to the ghw file |
1.0 |
open |
|
2016-07-25
|
2016-07-26
|
|
| 100 |
Can't use type as a selected name |
1.0 |
open |
|
2015-11-03
|
2015-11-03
|
|
| 91 |
More details when bound check failure at elaboration |
1.0 |
open |
|
2015-08-05
|
2015-09-22
|
|
| 79 |
Support basic VHDL-2008 hiearchical signal reference. |
1.0 |
open |
|
2015-05-21
|
2015-09-22
|
|
| 72 |
[VHDL08] aggregate with array elements |
1.0 |
open |
|
2015-05-19
|
2015-05-26
|
|
| 40 |
relax "choice must be locally static expression" |
1.0 |
open |
Tristan Gingold
|
2015-03-13
|
2015-03-17
|
|
| 25 |
[Feature Request] Elaboration flag to set 'severity' of PSL assertions |
1.0 |
open |
|
2014-11-04
|
2014-11-04
|
|
| 22 |
Analysis gives pointless warning 'universal integer bound must be numeric literal or attribute' |
1.0 |
open |
|
2014-06-27
|
2014-08-18
|
|
| 16 |
unexpected undefined signal |
1.0 |
open |
|
2014-05-16
|
2014-09-05
|
|
