I am having a problem with the gezel 8051 cosimulation hanging when the gezel code is continuously reading an address from the i8051buffer and the cpu will write to this address a start instruction.
The simulator goes to sleep thinking nothing can happen. The 8051 should wakeup the design when a write is made to the ram memory. This does not seem to be possible without large changes to the code.
Another fix would be:
bool i8051buffer::cannotSleepTest() {
return true;
}
This is what I am using now, the design will then never sleep if the i8051buffer is used.
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Anonymous
-
2011-12-11
That is correct. The i8051bufffer is shared memory with two independent read and write ports. It would require intercepting the write operations in i8051sim and triggering 'wakeup' when the software writes in any address of the shared range. The hooks are in the code (using register_addr, you can get a callback to external_write; cfr i8051systemsource) but this requires some coding.
If the end objective is hardware prototyping, it's worthwhile to think ahead about how you will map the model into synthesizable modules.
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Thanks for the pointer to register_addr, this should make a cleaner solution possible. I don't see why a process continuously reading a memory address on a dual port ram and then acting on it when it chages should not be synthesizable? I have already done this before using plain VHDL. The end result of this project will luckily not be used on a real fpga, I tried using fdlvhd to figure out how large the resulting design would be and the code had several syntax errors which I fixed manually but it is hard to verify if I fixed them correctly since all signals are named sig_xxx.
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Hello,
I am having a problem with the gezel 8051 cosimulation hanging when the gezel code is continuously reading an address from the i8051buffer and the cpu will write to this address a start instruction.
The simulator goes to sleep thinking nothing can happen. The 8051 should wakeup the design when a write is made to the ram memory. This does not seem to be possible without large changes to the code.
Another fix would be:
bool i8051buffer::cannotSleepTest() {
return true;
}
This is what I am using now, the design will then never sleep if the i8051buffer is used.
That is correct. The i8051bufffer is shared memory with two independent read and write ports. It would require intercepting the write operations in i8051sim and triggering 'wakeup' when the software writes in any address of the shared range. The hooks are in the code (using register_addr, you can get a callback to external_write; cfr i8051systemsource) but this requires some coding.
If the end objective is hardware prototyping, it's worthwhile to think ahead about how you will map the model into synthesizable modules.
Thanks for the pointer to register_addr, this should make a cleaner solution possible. I don't see why a process continuously reading a memory address on a dual port ram and then acting on it when it chages should not be synthesizable? I have already done this before using plain VHDL. The end result of this project will luckily not be used on a real fpga, I tried using fdlvhd to figure out how large the resulting design would be and the code had several syntax errors which I fixed manually but it is hard to verify if I fixed them correctly since all signals are named sig_xxx.