There are other tradeoffs that you are ignoring though.  For a given number of ALU’s the amount of “state” (register primarily, but this would also interact with inter-stage buffering) is clearly going to be greater in the G8x architecture (given number of ALU’s has to deal with roughly 5x the number of “threads”…)


I think both architectures are interesting.


Peter-Pike Sloan


From: [] On Behalf Of Marco Salvi
Sent: Thursday, February 14, 2008 10:39 AM
To: Game Development Algorithms
Subject: Re: [Algorithms] Dummie Matrix math questions


Umh..I can see your point and I can partially agree with it, but it's unlikely that G8x's instructions words are as long as R6xx.
I don't see why G8x couldn't efficiently work using far less instruction bandwidth than R6xx, even taking in consideration
the fact that G8x's ALUs are kind of 'double pumped'.
Terminology aside, I wouldn't be surprised if next architectures from AMD will be more similar to G8x than vice versa,
as it makes compilers job so much easier.


On Wed, Feb 13, 2008 at 9:45 AM, Emil Persson <> wrote:

Well, the shader cores are not vectors but scalar units, so calling it a scalar architecture makes perfect sense. Although VLIW would also be a valid description of it, if you prefer that. Personally I'm no big fan of the "VLIW" nomenclature since I suppose it's rather subjective at which point an instruction word becomes "very long" and it says little about the flexibility of the underlying hardware. I wouldn't be surprised if the G80's instruction words are "very long" too.