A short update on ATtiny4, ATtiny5, ATtiny9, ATtiny10, , ATtiny102 and ATtiny104 support.
A number of us Christos, Kent and I have been developing and testing the changes for the ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny102 and ATtiny104 chips. We have made a lot of progress hence this short update.
Overview
The ATtiny5, ATtiny9, ATtiny10, ATtiny102 and ATtiny104 are cool little chips but with very limited SRAM and not many SFRs.
1K Bytes of In-System Self-Programmable Flash, 32 Bytes Internal SRAM.
One16-bit Timer/Counter with PWM channels, 8-bit ADC, Analogy Comparator. Up to 12 MIPS throughput at 12 MHz. 1.8 - 5.5 V operations.
6 pin device for the little ones (14 for the 104)
Flash (Kbytes) 1
SRAM (Bytes) 32
Max I/O Pins 4 or 12
F.max (MHz) 12
Vcc (V) 1.8-5-5V
Analog Comparator Yes
4 channel ADC
The most significant change is that the AVRtiny processor core omits registers R0–R15. The registers are also not memory-mapped, with I/O ports from 0–63 and general-purpose RAM beginning at address 64(0x40).
The 16-bit arithmetic operations (ADIW, SBIW) are omitted, and many many more instructions omited, as are the load/store with displacement addressing modes (Y+d, Z+d), but the predecrement and postincrement addressing modes are retained.
The LPM instruction is omitted; instead program ROM is mapped to the data address space and may be accessed with normal load instructions.
Finally, the AVRtiny core deletes the 2-word LDS and STS instructions for direct RAM addressing, and instead uses the opcode space previously assigned to the load/store with displacement instructions for new 1-word LDS and STS instructions which can access the first 128 locations of general-purpose RAM, addresses 0x40 to 0xBF. (The IN and OUT instructions provide direct access to I/O space from 0 to 0x3F.)
Progress
We have the basics operational. We have two major issues to resolve but they should be resolvable once I get clarity from Microchip and a little help from Hugh,
We have created a series of demos to test our progress. These demos have been crucial to the work as they are testing the major components. We have tried to cover the bases but considering we have very limited SRAM this is pretty cool.
Test Bit support - BitwiseControl.gcb
Basic If-then etc - FlowControl.gcb
Interrupt support - Interrupt_LEDs_for_1second.gcb
PWM support - PMWDutyChanger.gcb
Macro support - Pulse_LED_for_1second.gcb
Macro support- Pulseout_LEDs_for_1second.gcb
Sub/Function support - Simple_LED_flash_for_1second.gcb
Input/Output support - Simple_Logic_to_Set_LEDS.gcb
Serial support -SoftwareSerial.gcb
Timers and Watchdog support - Timer_Delay_using_Watchdog.gcb
ADC support - Tiny10_ReadAnologue_to_SetPWMDuty.gcb
Changes to compiler and libaries
To get the chips to work means substantial changes to the compiler, and the libraries. We have updated the following:
system.h - support for string, osc etc
usart.h - changed memory addressing to support these chips
pwm.h - changed memory addressing to support these chips
string.h - major changes to memory addressing to support these chips
Compiler - major changes to support memory, SFR address and the new chipfamily.
Chip Family - We have introduced a new chipfamily, called 121, to support the chips.
DAT files. - We have all new .dat files with new parameters.
So what? This means that you MUST have v0.98.07 RC18 or greater to get support for these chips. There is NO support in previous versions.
State of play
We have two issues.
Microchip have not yet provided the correct informtion for us to create (and validate) the generation of a HEX file. Currently, we can generate a HEX file - it works. But, the configuration was determined by empirical testing NOT from the Microchip document. We are confident regarding the empirical testing as we have implemented cross-compiling into Atmel Studio (only needed during testing).
We have an issue were we running out of SFRs. This is resolvable in the compiler but this may take a day or two.
Summary
We have made huge progress and we think we can add a new chip family to Great Cow BASIC.
Got one of these chips? wanna play... let us know.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
We have updated the core compiler and USART library to support serial in operations and to properly support serial interupts. These chips require specific method to write to the USART registers. Hidden away in the datasheet is a statement that use of clear and setting of bits in the USART registers is not supported.
The update to the compiler now handles these register writes correctly.
The latest compiler is dated 7/7/2020.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
A short update on ATtiny4, ATtiny5, ATtiny9, ATtiny10, , ATtiny102 and ATtiny104 support.
A number of us Christos, Kent and I have been developing and testing the changes for the ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny102 and ATtiny104 chips. We have made a lot of progress hence this short update.
Overview
The ATtiny5, ATtiny9, ATtiny10, ATtiny102 and ATtiny104 are cool little chips but with very limited SRAM and not many SFRs.
The most significant change is that the AVRtiny processor core omits registers R0–R15. The registers are also not memory-mapped, with I/O ports from 0–63 and general-purpose RAM beginning at address 64(0x40).
The 16-bit arithmetic operations (ADIW, SBIW) are omitted, and many many more instructions omited, as are the load/store with displacement addressing modes (Y+d, Z+d), but the predecrement and postincrement addressing modes are retained.
The LPM instruction is omitted; instead program ROM is mapped to the data address space and may be accessed with normal load instructions.
Finally, the AVRtiny core deletes the 2-word LDS and STS instructions for direct RAM addressing, and instead uses the opcode space previously assigned to the load/store with displacement instructions for new 1-word LDS and STS instructions which can access the first 128 locations of general-purpose RAM, addresses 0x40 to 0xBF. (The IN and OUT instructions provide direct access to I/O space from 0 to 0x3F.)
Progress
We have the basics operational. We have two major issues to resolve but they should be resolvable once I get clarity from Microchip and a little help from Hugh,
We have created a series of demos to test our progress. These demos have been crucial to the work as they are testing the major components. We have tried to cover the bases but considering we have very limited SRAM this is pretty cool.
Test Bit support - BitwiseControl.gcb
Basic If-then etc - FlowControl.gcb
Interrupt support - Interrupt_LEDs_for_1second.gcb
PWM support - PMWDutyChanger.gcb
Macro support - Pulse_LED_for_1second.gcb
Macro support- Pulseout_LEDs_for_1second.gcb
Sub/Function support - Simple_LED_flash_for_1second.gcb
Input/Output support - Simple_Logic_to_Set_LEDS.gcb
Serial support -SoftwareSerial.gcb
Timers and Watchdog support - Timer_Delay_using_Watchdog.gcb
ADC support - Tiny10_ReadAnologue_to_SetPWMDuty.gcb
Changes to compiler and libaries
To get the chips to work means substantial changes to the compiler, and the libraries. We have updated the following:
system.h - support for string, osc etc
usart.h - changed memory addressing to support these chips
pwm.h - changed memory addressing to support these chips
string.h - major changes to memory addressing to support these chips
Compiler - major changes to support memory, SFR address and the new chipfamily.
Chip Family - We have introduced a new chipfamily, called 121, to support the chips.
DAT files. - We have all new .dat files with new parameters.
So what? This means that you MUST have v0.98.07 RC18 or greater to get support for these chips. There is NO support in previous versions.
State of play
We have two issues.
Summary
We have made huge progress and we think we can add a new chip family to Great Cow BASIC.
Got one of these chips? wanna play... let us know.
Latest update.
We have updated the core compiler and USART library to support serial in operations and to properly support serial interupts. These chips require specific method to write to the USART registers. Hidden away in the datasheet is a statement that use of clear and setting of bits in the USART registers is not supported.
The update to the compiler now handles these register writes correctly.
The latest compiler is dated 7/7/2020.