GCB will not compile ASM that contains "BANKSEL" Directive.

[William Roth]

Problem:
The Compiler will return a syntax error on any line that contains BANKSEL directive.
GCB.exe is FEB 5, 2015

Example Code: (DOES NOT COMPILE)

'Set chip model:
#chip 16F1788, 16
#config LVP = Off
#config PLLEN = OFF

Dir PORTA.0 Out

 Do

        banksel PORTA
        bsf PORTA,0
        bcf PORTA,0    


 Loop   

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If banksel PORTA line is removed, the code will compile and the compiler will add the banksel to the final ASM code.
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[Hugh Considine]

To produce (what it thinks is) the best placement of banksel statements, the compiler needs to be able to add and delete them as needed. It doesn't currently have any way to take into account banksel statements placed by the user.

If you need to force a banksel into the assembly, try this:

asm banksel PORTA

But as a general rule, I'd suggest not doing this. The compiler should place the banksel statements where they are needed, and if it isn't then that's a separate bug that needs fixing. The compiler won't detect the presence of the forced banksel, and will automatically add another one before or after it.

(And also, keeping banksel out of the code does make it slightly more portable between 16F and 18F chips. An 18F running that code wouldn't need a banksel before the PORTA access.)

Is there a specific reason why banksel is needed there?

[William Roth]

Thanks Hugh

I looked at the ASM produced by GCB and then attempted to insert it in line for testing. Thus the compile/syntax error.

I have PIC ASM code from the past (before I started with GCB) and was doing this to test the feasibility of inserting sections of my past work into some GCB programs, rather than manually porting to GCB. The ASM code spans from 12F to 18F PIC.

Are there any other "Gotchas" that I may need to know about ?

[kent_twt4]

Here is some code that I used for the 18f26k22. It has more than 256 SFR's, so ACCESS doesn't work.

Don't get into assembly much, or poke around the GCB inner workings. To get beyond the 256 SFR's I used both the banksel and BSR it appears. Couldn't say for sure if this code was even a working example? CCP1 is within standard ACCESS range.

#chip 18f26k22, 64

#config MCLRE=INTMCLR, OSC=INTIO67, BOREN=OFF,  PBADEN=OFF, CCP2MX=PORTB3   ',CCP3MX=PORTC6 


#define blank PortC.7
#define led1 PortA.5
#define gsclk PortC.2   'CCP1 output
#define TMR3CLK PortC.0 'T2CKI pin fed from CCP1 PWM

dir TMR3CLK in
dir blank out
dir led1 out
dir gsclk out
dir PortB.3 out
dir PortC.1 out
dir PortB.5 out
dir PortC.6 out
dir PortB out
OSCCON = 112    '96=8Mhz NOTICE 112=16MHz current default of GCBasic
Set PLLEN ON    'enable INTOSC PLL (8 or 16MHZ)


'*********** CCP1 *********************
'sets 50% PWM duty cycle (CCP1X,Y = 0), i.e. 1 clk of 2 clk period
CCP1CON = b'00001100'   'setup PWM mode
'set up hardware PWM with bare minimum values
PR2 = 50        'TMR2 period value, i.e. 2 instr. clks, approx. 8MHz
CCPR1L = 1  'set for approx. 80% Duty cycle
Set DC1B1 On
Set DC1B0 Off

'dim TMRONE as word alias TMR1H, TMR1L
'Use CCP1 PWM as Timer3 clock input (T3CKI) PortC.0
'T3CON = b'10000000'            ;Clock source from T3CKI, no prescale, secondary OSC enabled, sync system clock, 8 bit r/w
'T3GCON = b'10000000'   'Enable TMRx count control by gate, source is TMR3 gate pin
'With PR2=1 CCP1 is about 8MHz with 16Mhz instr cycle (64/4)
'Preload TMR1 for approx. 4096*(1/8000000)/16000000= 8192 cycles
'TMR1 FFFF-1FFF=E000
'TMRONE = 0xE000

'T4CON = b'00000100'
'Set TMR4ON ON
'HPWM 2, 200, 50    '2000kHz= not quite 2Mhz on scope
'Try using CCP3 as periodic interrupt with TMR3? no preload TMR3 in ISR everytime

'*********** CCP2 *********************
    movlw   12      ;std PWM mode
    movwf   CCP2CON,ACCESS
    movlw   8       ;set CCP2 PWM timer as TMR4
    asm banksel CCPTMRS0
    iorwf   CCPTMRS0
    movlw   50      ;50 instr cycles * 16 prescale * 1/16000000 = 50 us or freq. of 20kHz
    asm banksel PR4
    movwf   PR4
    movlw   20      ;40% D.C. with PR4=50: 20 (instr cycles) * 16 (prescale) * 1/16000000 = 20 us
    movwf   CCPR2L,ACCESS
    movlw   7       ;Prescale is 16, TMR4ON=1
    asm banksel T4CON
    movwf   T4CON


'T2CON = b'10000000'            ;Clock source from T3CKI, no prescale, secondary OSC enabled, sync system clock, 8 bit r/w
'T2GCON = b'10000000'   'Enable TMRx count control by gate, source is TMR3 gate pinCCPTMRS0 = b'00001000'   'CCP2 uses TMR3 or TMR4

'*********** CCP3 *********************
'try movff with W
    movlb 15
    'movwf BSR
    movlw   12      ;std PWM mode
    movlb 15
    'movwf BSR
    'asm banksel CCP3CON
    movff   W,CCP3CON

    'movlw 15
    'movwf BSR
    movlw   128     ;set CCP3 PWM timer as TMR6
    movlb   15
    'asm banksel CCPTMRS0
    movff   W,CCPTMRS0
    'iorwf  CCPTMRS0

    movlb 15
    'movwf BSR
    movlw   100     ;100 instr cycles * 16 prescale * 1/16000000 = 100 us or freq. of 10kHz
    'asm banksel PR6
    movlb 15
    movff   W,PR6

    'movwf BSR
    movlw   50      ;50% D.C. with PR4=100: 50 (instr cycles) * 16 (prescale) * 1/16000000 = 50 us
    'asm banksel    CCPR3L
    movlb 15
    movff   W,CCPR3L

    'movwf BSR
    movlw   7       ;Prescale is 16, TMR6ON=1
    movlb 15
    'asm banksel T6CON
    movff   W,T6CO
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