Setting OSC for specific PIC

[Moto Geek]

Looking at the chip data file for a pic16f15325, if I want to use an external 20Mhz crystal, in GCB, would I use this...
#chip 16f15325, 20
#config MCLRE = OFF, WDT = Off, OSC = HS

or

#chip 16f15325, 20
#config MCLRE = OFF, WDT = OFF, FEXTOSC = HS

or
something else altogether.

This is what the Chip Data has listed, so I just want to make sure that we have to write the config lines using what is in the chip data file. Or when I write OSC in the config, GCB automatically knows what I'm talking about.

FEXTOSC=LP,XT,HS,RESERVED,OFF,ECL,ECM,ECH

Thanks!!!

[Anobium]

Very good start - come back and ask if you need to.

Can someone verify in MPLAB-IDE? That is always a good cross check. I am not near computer today.

[Anobium]

Here is a more completed init sequence. Note the setting for the OSCCONx at the bottom.

Essentially, you need to add config items relating to the clock and the bottom OSCCONx section (at the bottom). These parameters should work, but, they still may need some tweaking for a 20mhz clock.

' CONFIG1
#config FEXTOSC = HS    ' External Oscillator mode selection bits->HS (crystal oscillator) above 4MHz PFM set to high power
#config RSTOSC = EXT1X    ' Power-up default value for COSC bits->EXTOSC operating per FEXTOSC bits
#config CLKOUTEN = OFF    ' Clock Out Enable bit->CLKOUT function is disabled i/o or oscillator function on OSC2
#config CSWEN = ON    ' Clock Switch Enable bit->Writing to NOSC and NDIV is allowed
#config FCMEN = ON    ' Fail-Safe Clock Monitor Enable bit->FSCM timer enabled

' CONFIG2
#config MCLRE = ON    ' Master Clear Enable bit->MCLR pin is Master Clear function
#config PWRTE = OFF    ' Power-up Timer Enable bit->PWRT disabled
#config LPBOREN = OFF    ' Low-Power BOR enable bit->ULPBOR disabled
#config BOREN = ON    ' Brown-out reset enable bits->Brown-out Reset Enabled, SBOREN bit is ignored
#config BORV = LO    ' Brown-out Reset Voltage Selection->Brown-out Reset Voltage (VBOR) set to 1.9V on LF, and 2.45V on F Devices
#config ZCD = OFF    ' Zero-cross detect disable->Zero-cross detect circuit is disabled at POR.
#config PPS1WAY = ON    ' Peripheral Pin Select one-way control->The PPSLOCK bit can be cleared and set only once in software
#config STVREN = ON    ' Stack Overflow/Underflow Reset Enable bit->Stack Overflow or Underflow will cause a reset

' CONFIG3
#config WDTCPS = WDTCPS_31    ' WDT Period Select bits->Divider ratio 1:65536 software control of WDTPS
#config WDTE = OFF    ' WDT operating mode->WDT Disabled, SWDTEN is ignored
#config WDTCWS = WDTCWS_7    ' WDT Window Select bits->window always open (100%) software control keyed access not required
#config WDTCCS = SC    ' WDT input clock selector->Software Control

' CONFIG4
#config BBSIZE = BB512    ' ->512 words boot block size
#config BBEN = OFF    ' ->Boot Block disabled
#config SAFEN = OFF    ' ->SAF disabled
#config WRTAPP = OFF    ' ->Application Block not write protected
#config WRTB = OFF    ' ->Boot Block not write protected
#config WRTC = OFF    ' ->Configuration Register not write protected
#config WRTSAF = OFF    ' ->SAF not write protected
#config LVP = ON    ' Low Voltage Programming Enable bit->Low Voltage programming enabled. MCLR/Vpp pin function is MCLR.

' CONFIG5
#config CP = OFF    ' UserNVM Program memory code protection bit->UserNVM code protection disabled

    'NOSC EXTOSC NDIV 1 
    OSCCON1 = 0x70
    'CSWHOLD may proceed SOSCPWR Low power 
    OSCCON3 = 0x00
    'MFOEN disabled LFOEN disabled ADOEN disabled SOSCEN disabled EXTOEN disabled HFOEN disabled 
    OSCEN = 0x00
    'HFFRQ 4_MHz 
    OSCFRQ = 0x02
    'MFOR not ready 
    OSCSTAT = 0x00
    'HFTUN 0 
    OSCTUNE = 0x00