18f25k80 configuration setting confusion

[David Stephenson]

On the 18F25k80 there appears to be two registers that set the oscillator configuration. This has me confused.
The OSCCON, IRCF bits and the CONFIG1H, FOSC bits They both appear to do much the same thing. There is also the PLL enable which seems to appear twice in OSCTUNE, IRCF and in CONFIG1H,PLLEN.
Can somebody explain how to configure this chip? I want to run at 64 MHz.

[kent_twt4]

Normally you would think that the PLLEN would have to be set in config. But the data sheet says with the INTOSC only the PLLEN bit of the OSCTUNE register needs to be set. I would expect the internal osc high frequency bit to be set by default. Here is the setup from the archive for the 18f26k22 device, adjust accordingly for the 18f25k80 by looking up the chipdata file and data sheet.

'Chip model  
#chip 18F26K22,64
#config MCLRE=EXTMCLR, OSC=INTIO67, LVP=Off,BOREN=OFF, PBADEN=ON

Set PLLEN On
OSCCON = 112  '96=8Mhz NOTICE 112=16MHz current default of GCBasic

[David Stephenson]

Thanks I should have looked at the oscillator chapter rather than the registers.
"the PLLCFG is ignored". # CONFIG OSC=INITO2 is the oscillator setting.

[William Roth]

@David

There is no need to mess about with IRCF bits or PLL settings when using the internal OSC. That is the job of system.h and one of the main reasons to use GCB or any other high level language. There should be no confusion here.

The 18F25K80 uses different names for config options than 18F25K22 so Kent's solution will not work.

The first thing I do when setting up a PIC chip that I am not familoar with is to open up its GCB datfile and look at the [confgops] section. This shows the OSC config options. For the 18F25K80 they are:

INTOSCSEL_LOW
INTOSCSEL_HIGH
LP
XT
HS2
HS1
EC3IO
EC3
RC
RCIO
INTIO2
INTIO1
EC2IO
EC2
EC1IO
EC1.

Refering to the dataheet we need to use either INTIO1 or INTIO2. INTIO1 Enables Clockout INTIO2 does not. We DO NOT need to know the ICRF bits or the PLL stuff.

So the basic Configuration becomes:

#Chip 18f25K80, 64        '// sets IRCF/PLL bits and delay timing
#config OSC = INTIO1      '// Internal OSC with Clockout on pin 10
'// #config OSC = INTIO2  '// Internal OSC with no Clockout
#Config MCLRE = OFF      '// Assure Chip starts after programming

  Do

 Loop

.
.

Now compile this and progran your chip and look at pin 10 with your scope. It should be 16 Mhz which indicates that the chip is operting at 64 Mhz (16 x 4)

[David Stephenson]

Yes I have got it working now. I made an interesting mistake of wiring it up like a 16F1788 and guess what the 18F25K80 does not have a porta.4 pin so my code was not functioning because it required an input on porta.4.
Going through the datasheet the instruction set has conditional branches (BZ and BNZ) seems like they could save some code if only I understood how they worked.

[Chris Roper]

Going through the datasheet the instruction set has conditional branches (BZ and BNZ) seems like they could save some code if only I understood how they worked.

They are Relative Branch instructions.
They test the Z flag and jump +/- 127 instructions relative to the current instruction.

But why would you use them in a GCBASIC program?

GCBASIC is great at handling inline assembler but it is hardly ever needed as the code it generates is already optimised.

If you are writing something that will require relative jumps you would need to be able to calculate the offsets and would be better off using MPLAB and MPASM.