ADC clock source

[David Stephenson]

How does GCBasic select the Fosc divider for the ADC clock?
I'm looking at the ASM file and it is so congested with select cases that I can't easily see what is going on.
My oscilloscope is giving about 40 us conversion yet I should be able to get less than 20us (even less if I go outside the "recommended" range). I am using a 16F1788 at 32 MHz.

[Anobium]

What version of Compiler? Have you enabled the ADC optimisation?
We do have a much improved library available. This handles conversion timing correctly.

[Anobium]

CONVERSION CLOCK

We select the source of the conversion clock via the ADCS bits of the ADC register.

There are seven possible clock options, they are:

• FOSC/2
• FOSC/4
• FOSC/8
• FOSC/16
• FOSC/32
• FOSC/64
• FRC (dedicated internal FRC oscillator)

The conversion clock setting option are:

• The default is MediumSpeed which equates to FOSC/16
• If ADSpeed HighSpeed is set then FOSC/2 is selected
• If ADSpeed MediumSpeed is set then FOSC/16 is selected
• If ADSpeed LowSpeed is set then FOSC/32 is selected
• If ADSpeed InternalClock is set then FRC is selected

See table 17-1 of the datasheet for the specific Tad (timings) for your specific microcontroller.

SETTING ADDITIONAL REGISTER OR REGISTER BITS

Setting additional registers or register bits before the actual read operation can be enabled by using #define ADReadPreReadCommand.

For example to set the ADSpeed to FOSC/4 (which is not one of the standard options) simply add a the constant as folllows to your user code.

#define ADReadPreReadCommand ADCS2=1:ADCS1=0:ADCS0=0 'select FOSC/4

The code defined by this constant will overwrite the library settings. These user insertion of code means you can use the library with the greatest flexibility.

OPTIMISATION

See http://gcbasic.sourceforge.net/help/_analog_digital_conversion_code_optimisation.html for the optimisation.

Optimisation will dramatically reduce the logic overhead of the ADC library.

Optimisation can remove over ~120 words from the generated ASM and the optimisation will tidy the code to make an easier review of the ASM.

LATEST LIBRARY

See attached.

DEBUGging

Adding #define DebugADC_H will place debug in the ASM to assist debugging.

[David Stephenson]

Thanks that's very illuminating.
Just for fun I will try to do a ADC read using ASM to see how easy it is.

The problem is that I have a device that is outputting data prompted by clock pulses from the microprocessor. The minimum clock rate is supposed to be 200 kHz (much too fast for the ADC to capture). I am hoping that I can push this clock rate a bit lower and things will still work, but I will also have to tweak the ADC timing to outside the recommeded range.
Yes an external ADC will solve this, but it will also make everthing much more complex.

[Anobium]

It was good to document these  ADC  features.  You can simply use Great Cow BASIC to generate the asm then paste into your main Where are you now? dropping the library. A good technique. You easily optimise further than our internal optimisation methods.

Sounds like you will be having fun.

[kent_twt4]

The 18fxx31 family has a 200ksps adc, probably others out there too. It makes my head hurt thinking about setting up what is a very complex adc module.

[David Stephenson]

This part of the ASM (below)created by GCASM seems to be causing an unnecessary delay.
My tests indicate that conversion does not begin until the ADCON0,GO_NOT_done bit is set so the delay before it is just adding some 20 us to the time it takes to get a reading.

ENDIF6
    banksel ADCON0
    bsf ADCON0,ADON
    movlw   2
    movwf   SysWaitTemp10US
    banksel STATUS
    call    Delay_10US '***delay here
    banksel ADCON0
    bsf ADCON0,GO_NOT_DONE
    nop
SysWaitLoop1
    btfsc   ADCON0,GO_NOT_DONE
    goto    SysWaitLoop1
    bcf ADCON0,ADON

 **   I've got coversion down to 18 us (any less and the reading quality is compromised).

    It turned out to be not as difficult as it looks (as ever the datasheet obfuscates)
  **
    dim q1h(255)
    dim q1l(255)
    adcon0=b'00001100' '7 12bit, 6-2 pin,1 active,0 EN
adcon1=b'10100000'
adcon2=b'00001111'

start:
i=0
do
i=i+1
if i=255 then exit do
set porta.5 on
bsf adcon0,adon
nop
nop
nop
bsf ADCON0,GO_NOT_DONE
wait 5 us
WaitLoop1:
btfsc   ADCON0,GO_NOT_DONE
goto    WaitLoop1
bcf ADCON0,ADON
clrf    ANSELA
clrf    ANSELB
clrf    ANSELC
set porta.5 off
q1l(i)=adresl
q1h(i)=adresh
bcf adcon0,adon
loop

for i=1 to 255
i2cstart
i2csend(0x44) 'write to USB
i2csend (q1h(i))
i2csend (q1l(i))
i2csend i
i2cstop
wait 200 ms
next i

goto start

[stan cartwright]

@David...It's not just me then.. :) Fastest sampleing is interesting.

[Anobium]

I understand it is faster from your testing. Can you explain how? Sounds like it is 2us faster overall.

Some comments in the ADC code may help me and others in the future. Anything with ADCONn it worth explaining as the bits are different across the range of chips.

[David Stephenson]

Originally it took 40 us. I've got it down to 18 us.
The problem seems to be that the orginal code (generated by GCB) has a 20 us delay between
BSF ADCON0,ADON and
BSF ADCON0,GO_NOT_DONE which is causing the extra time for conversion.

[Anobium]

I see. The wait command. We should review to understand the impact on adapting the library.

[William Roth]

Can anyone show me in the datasheet where it says it is necessaty to turn the ADC module on/of between each read /aquisition?

I get where it may be desireable to turn off the module to save power when adc reads are infrequent. But is this really necessary in all cases?

It seem to me that there are several unnecessary delays in the ADC stuff. The converstion starts when the the GO_DONE bit is set in software and ends when the GO_DONE bit automtically clears when the conversionis complete. The conversion time is determined by the ADC clock setting and the ADC resolution (10-bit or 12-bit with this particular chip). It should be easy enough to poll the GO_DONE bit and then read the ADRESL/H registers on the next instruction. There should be no need to add any artifical delays unless specifically called for in the datasheet.

As far as the ADC clock setting goes ( I am refering to the AD-H library), for optimal performance it should be parametric to to the system clock speed and based upon the Chart in the Datasheet. If the clock is at 32 MHz and we assume a 12-bit ADC, then the ADC Clock should be set to FOSC/32 to allow for a 15 T(ad) conversion. Having the ADC clock permanently set to FOSC/8 or any other setting other than the built in internal ADC clock will likely result in less than optimal performance in certain cases.

[Anobium]

Only Hugh can state the initial design intent of turning off the module. We have maintained the approach over the years.

[William Roth]

My guess is that it was done based upon the limited selection of chips at the time and where speed was not much of a concern. It is extremely rare for an application to require a 200KHz ADC sampling rate ( which should be done with an external ADC device).

I can tweak the 16F1788 to give seemingly accurate 12-bit reads down to about a 9us conversion time, but this is outside of the chip's specification. And, of course, the ADH library is not used at all.

[stan cartwright]

William sir,I read your posts for info.
I wonder if 3rd party info, generally arduino sites, is valid, ie running adc above data sheet maximum, whole projects based around the idea.
I guess using an external a-d chip is pointless without a fast buffer to store it but with limited hardware and 8 bit ucontroller maybe make equivelent of £15 ebay scope kit.